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CY7C43684AV-10AC

3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO with Bus Matching

Cypress Semiconductor 

CY7C43644AV

CY7C43664AV

CY7C43684AV

Functional Description

The CY7C436X4AV is a monolithic, high-speed, low-power,

CMOS Bidirectional Synchronous FIFO memory which

supports clock frequencies up to 133 MHz and has Read

access times as fast as 6 ns. Two independent 1K/4K/16K ×

36 dual-port SRAM FIFOs on board each chip buffer data in

opposite directions. FIFO data on Port B can be input and

output in 36-bit, 18-bit, or 9-bit formats with a choice of Big or

Little Endian configurations.

The CY7C436X4AV is a synchronous (clocked) FIFO,

meaning each port employs a synchronous interface. All data

transfers through a port are gated to the LOW-to-HIGH

transition of a port clock by enable signals. The clocks for each

port are independent of one another and can be asynchronous

or coincident. The enables for each port are arranged to

provide a simple bidirectional interface between micropro-

cessors and/or buses with synchronous control.

Communication between each port may bypass the FIFOs via

two mailbox registers. The mailbox registers’ width matches

the selected Port B bus width. Each mailbox register has a flag

(MBF1 and MBF2) to signal when new mail has been stored.

Two kinds of reset are available on the CY7C436X4AV: Master

Reset and Partial Reset. Master Reset initializes the Read and

Write pointers to the first location of the memory array,

configures the FIFO for Big or Little Endian byte arrangement

and selects serial flag programming, parallel flag

programming, or one of the three possible default flag offset

settings, 8, 16, or 64. Each FIFO has its own independent

Master Reset pin, MRS1 and MRS2.

Partial Reset also sets the Read and Write pointers to the first

location of the memory. Unlike Master Reset, any settings

existing prior to Partial Reset (i.e., programming method and

partial flag default offsets) are retained. Partial Reset is useful

since it permits flushing of the FIFO memory without changing

any configuration settings. Each FIFO has its own,

independent Partial Reset pin, PRS1 and PRS2.

The CY7C436X4AV have two modes of operation: In the CY

Standard mode, the first word written to an empty FIFO is

deposited into the memory array. A Read operation is required

to access that word (along with all other words residing in

memory). In the First-Word Fall-Through mode (FWFT), the

first long-word (36-bit wide) written to an empty FIFO appears

automatically on the outputs, no Read operation required

(nevertheless, accessing subsequent words does necessitate

a formal Read request). The state of the BE/FWFT pin during

FIFO operation determines the mode in use.

Each FIFO has a combined Empty/Output Ready flag (EFA/

ORA and EFB/ORB) and a combined Full/Input Ready flag

(FFA/IRA and FFB/IRB). The EF and FF functions are selected

in the CY Standard mode. EF indicates whether the memory

is empty and FF indicates whether the FIFO memory is full.

The IR and OR functions are selected in the First-Word Fall-

Through mode. IR indicates whether or not the FIFO has

available memory locations. OR shows whether the FIFO has

data available for reading or not. It marks the presence of valid

data on the outputs.

Each FIFO has a programmable Almost Empty flag (AEA and

AEB) and a programmable Almost Full flag (AFA and AFB).

AEA and AEB are asserted when a selected number of words

written to FIFO memory achieve a predetermined “almost

empty state.” AFA and AFB are asserted when a selected

number of words written to the memory achieve a predeter-

mined “almost full state.” [2]

IRA, IRB, AFA, and AFB are synchronized to the port clock that

writes data into its array. ORA, ORB, AEA, and AEB are

synchronized to the port clock that reads data from its array.

Programmable offset for AEA, AEB, AFA, and AFB are loaded

in parallel using Port A or in serial via the SD input. Three

default offset settings are also provided. The AEA and AEB

threshold can be set at 8, 16, or 64 locations from the empty

boundary and AFA and AFB threshold can be set at 8, 16, or

64 locations from the full boundary. All these choices are made

using the FS0 and FS1 inputs during Master Reset.

Two or more devices may be used in parallel to create wider

data paths. A Retransmit feature is available on these devices.

The CY7C436X4AV FIFOs are characterized for operation

from 0°C to 70°C commercial, and from –40°C to 85°C indus-

trial. Input ESD protection is greater than 2001V, and latch-up

is prevented by the use of guard rings.

Selection Guide

CY7C43644/64/84AV CY7C43644/64/84AV CY7C43644/64/84AV

–7

–10

–15

Unit

Maximum Frequency

133

100

66.7

MHz

Maximum Access Time

6

8

10

ns

Minimum Cycle Time

7.5

10

15

ns

Minimum Data or Enable Set-Up

3

4

5

ns

Minimum Data or Enable Hold

0

0

0

ns

Maximum Flag Delay

6

8

10

ns

Active Power Supply

Commercial

60

60

60

mA

Current (ICC1)

Industrial

60

Note:

2. When FIFO is operated at the almost empty/full boundary, there may be an uncertainty of up to two clock cycles for flag deassertion, but the flag will always

be asserted exactly when the FIFO content reaches the programmed value. Use the assertion edge for trigger if flag accuracy is required. Refer to Cypress’s

application note entitled “Designing with CY7C436xx Synchronous FIFOs” for more details on flag uncertainties.

Document #: 38-06025 Rev. *C

Page 3 of 37

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