CY7C135-15(2004) Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C135-15
(Rev.:2004)

4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores

Cypress Semiconductor 

CY7C135

CY7C1342

Switching Waveforms

Read Cycle No. 1[14,15]

ADDRESS

DATA OUT

tOHA

PREVIOUS DATA VALID

Either Port Address Access

tRC

tAA

DATA VALID

Read Cycle No. 2[14,16]

[13]

SEM or CE

OE

DATA OUT

tPU

ICC

ISB

Either Port CE/OE Access

tACE

tLZOE

tLZCE

tDOE

tHZOE

DATA VALID

Read Timing with Port-to-Port[17]

ADDRESSR

R/WR

DATAINR

twc

MATCH

tPWE

tSD

tHD

VALID

tHZCE

tPD

1342–9

1342–10

ADDRESSL

MATCH

DATAOUTL

Notes:

14. R/W is HIGH for read cycle.

15. Device is continuously selected, CE = VIL and OE = VIL.

16. Address valid prior to or coincident with CE transition LOW.

17. CEL = CER =LOW; R/WL = HIGH

tDDD

tWDD

VALID

1342–11

Document #: 38-06038 Rev. *B

Page 6 of 12

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