CY7C135-15(2004) Просмотр технического описания (PDF) - Cypress Semiconductor
Номер в каталоге
Компоненты Описание
Список матч
CY7C135-15
(Rev.:2004)
(Rev.:2004)
Cypress Semiconductor
CY7C135-15 Datasheet PDF : 12 Pages
| |||
CY7C135
CY7C1342
Switching Characteristics Over the Operating Range[7, 8]
7C135–15 7C135–20 7C135–25 7C135–35 7C135–55
7C1342–15 7C1342–20 7C1342–25 7C1342–35 7C1342–55
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
tAA
tOHA
Read Cycle Time
Address to Data Valid
Output Hold From
Address Change
15
20
25
35
55
ns
15
20
25
35
55 ns
3
3
3
3
3
ns
tACE
CE LOW to Data Valid
tDOE
tLZOE[9,10,11]
tHZOE[9,10,11]
tLZCE[9,10,11]
tHZCE[9,10,11]
tPU[11]
tPD[11]
OE LOW to Data Valid
OE Low to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power Up
CE HIGH to Power Down
WRITE CYCLE
15
20
25
35
55 ns
10
13
15
20
25 ns
3
3
3
3
3
ns
10
13
15
20
25 ns
3
3
3
3
3
ns
10
13
15
20
25 ns
0
0
0
0
0
ns
15
20
25
35
55 ns
tWC
Write Cycle Time
15
20
25
35
55
ns
tSCE
CE LOW to Write End
12
15
20
30
50
ns
tAW
Address Set-Up to Write End 12
15
20
30
50
ns
tHA
Address Hold from Write End
2
2
2
2
2
ns
tSA
Address Set-Up to Write Start 0
0
0
0
0
ns
tPWE
Write Pulse Width
12
15
20
25
50
ns
tSD
Data Set-Up to Write End
10
13
15
15
25
ns
tHD
tHZWE[10,11]
tLZWE[10,11]
tWDD[12]
tDDD[12]
Data Hold from Write End
R/W LOW to High Z
R/W HIGH to Low Z
Write Pulse to Data Delay
Write Data Valid to Read
Data Valid
0
0
0
0
0
ns
10
13
15
20
25 ns
3
3
3
3
3
ns
30
40
50
60
70 ns
25
30
30
35
40 ns
SEMAPHORE TIMING[13]
tSOP
SEM Flag Update Pulse
10
10
10
15
15
ns
(OE or SEM)
tSWRD
SEM Flag Write to Read Time 5
5
5
5
5
ns
tSPS
SEM Flag Contention Window 5
5
5
5
5
ns
Notes:
7. See the last page of this specification for Group A subgroup testing information.
8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
9. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
10. Test conditions used are Load 3.
11. This parameter is guaranteed but not tested.
12. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.
13. Semaphore timing applies only to CY7C1342.
Document #: 38-06038 Rev. *B
Page 5 of 12
Share Link: