CY7C130A Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C130A

1 K × 8 Dual-Port Static RAM

Cypress Semiconductor 

CY7C130, CY7C130A

CY7C131, CY7C131A

Switching Waveforms (continued)

Figure 8. Write Cycle No. 1 (OE Three-States Data I/Os—Either Port[36, 37]

ADDRESS

Either Port

tWC

CE

R/W

DATAIN

tSCE

tAW

tHA

tSA

tPWE

tSD

tHD

DATA VALID

OE

DOUT

ADDRESS

CE

R/W

DATAIN

DATAOUT

tHZOE

HIGH IMPEDANCE

Figure 9. Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)[38, 39]

tWC

tSCE

tHA

tAW

tSA

tPWE

tHZWE

tSD

tHD

DATA VALID

tLZWE

HIGH IMPEDANCE

Notes

36. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal can

terminate a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.

37. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high impedance

and for data to be placed on the bus for the required tSD.

38. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.

39. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.

Document Number: 38-06002 Rev. *H

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