CY7C026A-15AXI Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C026A-15AXI

16K x 16 Dual-Port Static RAM

Cypress Semiconductor 

CY7C026A

Switching Waveforms

Figure 3. Read Cycle No.1 (Either Port Address Access)[18, 19, 20]

tRC

ADDRESS

DATA OUT

tAA

tOHA

PREVIOUS DATA VALID

DATA VALID

tOHA

CE and

LB or UB

OE

DATA OUT

ICC

CURRENT

ISB

ADDRESS

UB or LB

CE

DATA OUT

Figure 4. Read Cycle No.2 (Either Port CE/OE Access)[18, 21, 22]

tACE

tDOE

tLZOE

tLZCE

tPU

tHZCE

tHZOE

DATA VALID

tPD

Figure 5. Read Cycle No. 3 (Either Port)[18, 20, 21, 22]

tRC

tAA

tOHA

tLZCE

tABE

tACE

tLZCE

tHZCE

tHZCE

Notes

18. R/W is HIGH for read cycles.

19. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads.

20. OE = VIL.

21. Address valid prior to or coincident with CE transition LOW.

22. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.

Document #: 38-06046 Rev. *G

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