CY7C026A-15AXI Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C026A-15AXI

16K x 16 Dual-Port Static RAM

Cypress Semiconductor 

CY7C026A

Switching Waveforms (continued)

Figure 6. Write Cycle No. 1: R/W Controlled Timing[23, 24, 25, 26]

tWC

ADDRESS

OE

[27,28]

CE

R/W

DATA OUT

DATA IN

tAW

tSA

tPWE[26]

NOTE 30

tHZWE[29]

tSD

tHA

tLZWE

tHD

tHZOE[29]

NOTE 30

ADDRESS

[27,28]

CE

R/W

DATA IN

Figure 7. Write Cycle No. 2: CE Controlled Timing[23, 24, 25, 31]

tWC

tAW

tSA

tSCE

tHA

tSD

tHD

Notes

23. R/W must be HIGH during all address transitions.

24. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB.

25. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.

26. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data

to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be

as short as the specified tPWE.

27. To access RAM, CE = VIL, SEM = VIH.

28. To access upper byte, CE = VIL, UB = VIL, SEM = VIH.

To access lower byte, CE = VIL, LB = VIL, SEM = VIH.

29. Transition is measured 500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested.

30. During this period, the I/O pins are in the output state, and input signals must not be applied.

31. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.

Document #: 38-06046 Rev. *G

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