CY7C144AV(2011) Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C144AV Datasheet PDF : 21 Pages
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CY7C144AV
CY7C006AV
AC Test Loads and Waveforms
OUTPUT
C = 30 pF
3.3 V
R1 = 590
R2 = 435
OUTPUT
RTH = 250
C = 30 pF
OUTPUT
VTH = 1.4 V
C = 5 pF
3.3 V
R1 = 590
R2 = 435
(a) Normal Load (Load 1)
3.0V
GND
(b) Thévenin Equivalent (Load 1)
ALL INPUT PULSES
10%
90%
90%
10%
3 ns
.
Switching Characteristics Over the Operating Range[8]
3 ns
(c) Three-State Delay (Load 2)
(Used for tLZ, tHZ, tHZWE & tLZWE
including scope and jig)
Parameter
Description
CY7C144AV
CY7C006AV
-25
Unit
Min
Max
READ CYCLE
tRC
tAA
tOHA
tACE[9]
tDOE
tLZOE[10, 11, 12]
tHZOE[10, 11, 12]
tLZCE[10, 11, 12]
tHZCE[10, 11, 12]
tPU[12]
tPD[12]
WRITE CYCLE
Read cycle time
Address to data valid
Output hold from address change
CE LOW to data valid
OE LOW to data valid
OE Low to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to power-up
CE HIGH to power-down
25
–
ns
–
25
ns
3
–
ns
–
25
ns
–
13
ns
3
–
ns
–
15
ns
3
–
ns
–
15
ns
0
–
ns
–
25
ns
tWC
tSCE[9]
Write cycle time
CE LOW to write end
25
–
ns
20
–
ns
tAW
Address valid to write end
20
–
ns
tHA
tSA[9]
Address hold from write end
Address set-up to write start
0
–
ns
0
–
ns
tPWE
Write pulse width
20
–
ns
tSD
Data set-up to write end
15
–
ns
Notes
8.
Test conditions assume signal
and 30-pF load capacitance.
transition
time
of
3
ns
or
less,
timing
reference
levels
of
1.5
V,
input
pulse
levels
of
0
to
3.0
V,
and
output
loading
of
the
specified
IOI/IOH
9. To access RAM, CE=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time.
10. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
11. Test conditions used are Load 3.
12. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy
waveform.
Document #: 38-06051 Rev. *E
Page 8 of 21
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