CY7C144AV(2011) Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C144AV
(Rev.:2011)

3.3V 8K/16K x 8 Dual-Port Static RAM

Cypress Semiconductor 

CY7C144AV

CY7C006AV

Switching Waveforms

Figure 1. Read Cycle No. 1 Either Port Address Access[19, 20, 21]

tRC

ADDRESS

DATA OUT

tAA

tOHA

PREVIOUS DATA VALID

DATA VALID

tOHA

CE

OE

DATA OUT

ICC

CURRENT ISB

ADDRESS

Figure 2. Read Cycle No. 2 Either Port CE/OE Access[19, 22, 23]

tACE

tDOE

tLZOE

tLZCE

tPU

tHZCE

tHZOE

DATA VALID

tPD

Figure 3. Read Cycle No. 3 Either Port[19, 21, 22, 23]

tRC

tAA

tOHA

CE

DATA OUT

tLZCE

tABE

tACE

tLZCE

Notes

19. R/W is HIGH for read cycles.

20. Device is continuously selected CE = VIL. This waveform cannot be used for semaphore reads.

21. OE = VIL.

22. Address valid prior to or coincident with CE transition LOW.

23. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.

Document #: 38-06051 Rev. *E

tHZCE

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