CY7C006A-20JXC(2013) Просмотр технического описания (PDF) - Cypress Semiconductor
Номер в каталоге
Компоненты Описание
Список матч
CY7C006A-20JXC Datasheet PDF : 22 Pages
| |||
CY7C006A
Capacitance
Parameter [5]
Description
CIN
COUT
Input Capacitance
Output Capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = 5.0 V
Max
Unit
10
pF
10
pF
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
5V
OUTPUT
C = 30 pF
R1 = 893
R2 = 347
OUTPUT
RTH = 250
C = 30 pF
OUTPUT
VTH = 1.4 V
C = 5 pF
5V
R1 = 893
R2 = 347
(a) Normal Load (Load 1)
(b) Thévenin Equivalent (Load 1)
(c) Three-State Delay (Load 2)
(Used for tLZ, tHZ, tHZWE, & tLZWE
including scope and jig)
Data Retention Mode
The CY7C006A is designed with battery backup in mind. Data
retention voltage and supply current are guaranteed over
temperature. The following rules ensure data retention:
1. Chip Enable (CE) must be held HIGH during data retention,
within VCC to VCC – 0.2 V.
2. CE must be kept between VCC – 0.2 V and 70% of VCC during
the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (4.5 V).
Timing
VCC
CE
Data Retention Mode
4.5V VCC 2.0V
4.5V
tRC
VCC to VCC – 0.2V
VIH
Parameter
ICCDR1
Test Conditions [6]
@ VCCDR = 2 V
Max Unit
1.5
mA
Notes
5. Tested initially and after any design or process changes that may affect these parameters.
6. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested.
Document Number: 38-06045 Rev. *G
Page 7 of 22
Share Link: 