CY7C006A-20JXC(2013) Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C006A-20JXC Datasheet PDF : 22 Pages
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CY7C007A16 K × 8 Dual-Port Static RAM
CY7C006A
16 K × 8 Dual-Port Static RAM
16 K × 8 Dual-Port Static RAM
Features
■ True dual-ported memory cells which allow simultaneous
access of the same memory location
■ 16 K × 8 organization (CY7C006A)
■ 0.35-micron CMOS for optimum speed/power
■ High-speed access: 20 ns
■ Low operating power
❐ Active: ICC = 180 mA (typical)
❐ Standby: ISB3 = 0.05 mA (typical)
■ Fully asynchronous operation
■ Automatic power-down
Logic Block Diagram
R/WL
CEL
OEL
8
I/O0L–I/O7L
I/O
Control
■ Expandable data bus to 16 bits or more using
Master/Slave chip select when using more than one
device
■ On-chip arbitration logic
■ Semaphores included to permit software handshaking
between ports
■ INT flags for port-to-port communication
■ Pin select for Master or Slave
■ Commercial temperature range
■ Available in 68-pin PLCC (CY7C006A), 64-pin TQFP
(CY7C006A)
■ Pb-free packages available
I/O
Control
R/WR
CER
OER
8
I/O0R–I/O7R
A0L–A13L
A0L–A13L
CEL
OEL
R/WL
SEML
BUSYL [1]
INTL
14
Address
Decode
14
True Dual-Ported
RAM Array
Interrupt
Semaphore
Arbitration
M/S
Address
14
Decode
14
A0R–A13R
A0R–A13R
CER
OER
R/WR
SEMR
[1] BUSYR
INTR
Note
1. BUSY is an output in master mode and an input in slave mode.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-06045 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 30, 2013
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