CY14B101J Просмотр технического описания (PDF) - Cypress Semiconductor
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CY14B101J Datasheet PDF : 31 Pages
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CY14C101J
CY14B101J
CY14E101J
Slave Device Address
Every slave device on an I2C bus has a device select address.
The first byte after START condition contains the slave device
address with which the master intends to communicate. The
seven MSBs are the device address and the LSB (R/W bit) is
used for indicating Read or Write operation. The CY14X101J
reserves two sets of upper 4 MSBs [7:4] in the slave device
Table 1. Slave device Addressing
address field for accessing Memory and Control Registers. The
accessing mechanism is described in Memory Slave Device.
The nvSRAM product provides two different functionalities:
Memory and Control Registers functions (such as serial number
and product ID). The two functions of the device are accessed
through different slave device addresses. The first four most
significant bits [7:4] in the device address register are used to
select between the nvSRAM functions.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
nvSRAM
Function Select
CY14X101J Slave Devices
1
0
1
0 Device Select ID A16 R/W Selects Memory
Memory, 128 K × 8
0
0
1
1
Device Select ID
X
R/W
Selects Control
Registers
Control Registers
- Memory Control Register, 1 × 8
- Serial Number, 8 × 8
- Device ID, 4 × 8
- Command Register, 1 × 8
Memory Slave Device
The nvSRAM device is selected for Read/Write if the master
issues the slave address as 1010b followed by two bits of device
select. If slave address sent by the master matches with the
Memory Slave device address then depending on the R/W bit of
the slave address, data is either read from (R/W = ‘1’) or written
to (R/W = ‘0’) the nvSRAM.
The address length for CY14X101J is 17 bits and thus it requires
3 address bytes to map the entire memory address location. To
save an extra byte for memory addressing, the 17th bit (A16) is
mapped to the slave address select bit (A0). The dedicated two
address bytes represent bit A0 to A15.
Figure 8. Memory Slave Device Address
handbook, halfpMagSe B
LSB
1 0 1 0 A2 A1 A16 R/W
Slave ID
Device MSB of
Select Address
Control Registers Slave Device
The Control Registers Slave device includes the Serial Number,
Product ID, Memory Control and Command Register.
The nvSRAM Control Register Slave device is selected for
Read/Write if the master issues the Slave address as 0011b
followed by two bits of device select. Then, depending on the
R/W bit of the Slave address, data is either read from (R/W = ‘1’)
or written to (R/W = ‘0’) the device.
Figure 9. Control Registers Slave Device Address
handbook, halfpMagSe B
LSB
0 0 1 1 A2 A1 X R/W
Slave ID
Device
Select
Table 2. Control Registers Map
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
Description
Memory
Control
Register
Serial Number
8 Bytes
Device ID
Reserved
Read/Write
Details
Read/Write Contains
Block
Protect Bits and Serial
Number Lock bit
Read/Write Programmable Serial
(Read only Number. Locked by
when SNL setting the Serial
is set) Number lock bit in the
Memory
Control
Register to ‘1’.
Read only Device ID is factory
programmed
Reserved Reserved
Document Number: 001-54050 Rev. *M
Page 7 of 31
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