CY14B101J Просмотр технического описания (PDF) - Cypress Semiconductor
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CY14B101J Datasheet PDF : 31 Pages
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CY14C101J
CY14B101J
CY14E101J
1-Mbit (128 K × 8) Serial (I2C) nvSRAM
1-Mbit (128 K × 8) Serial (I2C) nvSRAM
Features
■ 1-Mbit nonvolatile static random access memory (nvSRAM)
❐ Internally organized as 128 K × 8
❐ STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using I2C
command (Software STORE) or HSB pin (Hardware STORE)
❐
RECALL
RECALL)
to
or
SRAM initiated on power-up (Power-Up
by I2C command (Software RECALL)
❐ Automatic STORE on power-down with a small capacitor
(except for CY14X101J1)
■ High reliability
❐ Infinite read, write, and RECALL cycles
❐ 1 million STORE cycles to QuantumTrap
❐ Data retention: 20 years at 85 °C
■ High speed I2C interface[1]
❐ Industry standard 100 kHz and 400 kHz speed
❐ Fast-mode Plus: 1 MHz speed
❐ High speed: 3.4 MHz
❐ Zero cycle delay reads and writes
■ Write protection
❐ Hardware protection using Write Protect (WP) pin
❐ Software block protection for 1/4, 1/2, or entire array
■ I2C access to special functions
❐ Nonvolatile STORE/RECALL
❐ 8 byte serial number
❐ Manufacturer ID and Product ID
❐ Sleep mode
■ Low power consumption
❐ Average active current of 1 mA at 3.4 MHz operation
❐ Average standby mode current of 150 µA
❐ Sleep mode current of 8 µA
■ Industry standard configurations
❐ Operating voltages:
• CY14C101J: VCC = 2.4 V to 2.6 V
• CY14B101J: VCC = 2.7 V to 3.6 V
• CY14E101J: VCC = 4.5 V to 5.5 V
❐ Industrial temperature
❐ 8- and 16-pin small outline integrated circuit (SOIC) package
❐ Restriction of hazardous substances (RoHS) compliant
Overview
The Cypress CY14C101J/CY14B101J/CY14E101J combines a
1-Mbit nvSRAM[2] with a nonvolatile element in each memory
cell. The memory is organized as 128 K words of 8 bits each. The
embedded nonvolatile elements incorporate the QuantumTrap
technology, creating the world’s most reliable nonvolatile
memory. The SRAM provides infinite read and write cycles, while
the QuantumTrap cells provide highly reliable nonvolatile
storage of data. Data transfers from SRAM to the nonvolatile
elements (STORE operation) takes place automatically at
power-down (except for CY14X101J1). On power-up, data is
restored to the SRAM from the nonvolatile memory (RECALL
operation). The STORE and RECALL operations can also be
initiated by the user through I2C commands.
Configuration
Feature
AutoStore
Software STORE
Hardware STORE
CY14X101J1 CY14X101J2 CY14X101J3
No
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Logic Block Diagram
VCC VCAP
Serial Number
8x8
Manufacturer ID /
Product ID
Power Control
Block
Sleep
Memory Control Register
Command Register
Quantum Trap
128 K x 8
SDA
SCL
A2, A1
WP
2
I C Control Logic
Slave Address
Decoder
Control Registers Slave
Memory Slave
Memory
Address and Data
Control
SRAM
128 K x 8
STORE
RECALL
Notes
1. The I2C nvSRAM is a single solution which is usable for all four speed modes of operation. As a result, some I/O parameters are slightly different than those on
chips which support only one mode of operation. Refer to AN87209 for more details.
2. Serial (I2C) nvSRAM is referred to as nvSRAM throughout the datasheet.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-54050 Rev. *M
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 29, 2013
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