CXD2453Q
Serial Interface AC Characteristics
Item
SCTL setup time with respect to rise of SCLK
SCTL hold time with respect to rise of SCLK
SDAT setup time with respect to rise of SCLK
SDAT hold time with respect to rise of SCLK
SCLK pulse width
∗3 T: Master clock cycle (ns)
(Topr = –20 to +75°C, VDD = 3.3V ± 0.3V, VSS = 0V)
Symbol Min.
Typ.
Max.
ts0
8T∗3
—
—
th0
8T
—
—
ts1
4T
—
—
th1
4T
—
—
tw1
4T
—
—
Timing Definitions
ts0
th0
SCTL 50%
tw1
tw1
50%
SCLK
50%
ts1
th1
50%
SDAT
50%
(D15)
50% (D0)
–7–