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CS8416-CZ

192 kHz Digital Audio Interface Receiver

Cirrus Logic 

CS8416

autodetect software used in Cirrus Logic DSPs. If

the AES3 stream contains sync codes in the proper

format for IEC61937 or DTS data transmission, an

internal AUTODETECT signal will be asserted. If

the sync codes no longer appear after a certain

amount of time, autodetection will time-out and

AUTODETECT will be de-asserted until another

format is detected. In Hardware Mode, the AUDIO

pin is the logical OR of AUTODETECT and the re-

ceived channel status bit 1. In Software mode the

AUDIO pin is available through the GPO pins. Al-

so, the specific data or audio format found by the

autodetect module is available in register 0Bh. Ad-

ditionally, the Pc/Pd burst preambles are available

in registers 23h-26h. If non-audio data is detected,

the data is still processed exactly as if it were nor-

mal audio. The exception is the use of de-emphasis

auto-select feature which will bypass the de-em-

phasis filter if the input stream is detected to be

non-audio. It is up to the user to mute the outputs as

required.

RCBL

out

VLRCK

C, U

Output

Figure 9. C/U data outputs

RCBL goes high 2 frames after receipt of a Z pre-amble, and is high for 16 frames.

VLRCK is a virtual word clock, available through GPO pins, that can used to frame the C/U ouput.

VLRCK duty cycle is 50%. VLRCK frequency is always equal to the incoming frame rate.

If the serial audio output port is in master mode, VLRCK = OLRCK.

C, U transitions are aligned within ±1% of VLRCK period to VLRCK edges

Gain,

dB

0

T1 =

50us

-10

T2

=15us

F1

3.183

F2

10.61

Figure 10. De-emphasis filter

Frequency,

KHz

DS578PP2

19

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