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CS8416-CZZR

192 kHz Digital Audio Interface Receiver

Cirrus Logic 

CS8416

Pin Name

OMCK

RMCK

OSCLK

OLRCK

SDOUT

RXSEL1

RXSEL0

TXSEL1

TXSEL0

TX

NV/RERR

AUDIO

96KHZ

RCBL

C

U

Pin #

25

24

27

28

26

10

11

12

13

20

14

15

16

17

19

18

Pin Description

System Clock (Input) - OMCK System Clock Mode is enabled by a transition (rising edge active) on

OMCK after reset. When enabled, the clock signal input on this pin is automatically output through

RMCK on PLL unlock. See “OMCK System Clock Mode” on page 28.

Input Section Recovered Master Clock (Output) - Input section recovered master clock output

from the PLL. Frequency is 256x the sample rate (Fs) when the U pin is pulled down by a 47 kΩ

resistor to DGND. Frequency is 128x the sample rate (Fs) when the U pin is pulled up by a 47 kΩ

resistor to VL.

Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin

Serial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on the

SDOUT pin. Frequency will be the output sample rate (Fs)

Serial Audio Output Data (Output) - Audio data serial output pin. This pin must be pulled low to

DGND through a 47 kΩ resistor to place the part in Hardware Mode.

Receiver MUX Selector (Input) - Used to select which pin, RXP[3:0], is used for the receiver input.

TX Pin MUX SELECTION (Input) - Used to select which pin, RXP[3:0], is passed to the TX pin out-

put. If TX passthrough is not used, the user should set it to output one of the unused receiver inputs.

S/PDIF MUX Passthrough (Output) - Single-ended signal is resolved to full-rail, but is not de-jittered

before it is output. Output is set by TXSEL[1:0]. This pin is also used to select the type of phase

detector (PDUR) at reset. If TX passthrough is not used, the user should set it to output one of the

unused receiver inputs.

Non-Validity Receiver Error/Receiver Error (Output) - Receiver error indicator. NVERR is selected

by a 47 kΩ resistor to DGND. RERR is selected by a 47 kΩ resistor to VL.

Audio Channel Status Bit (Output) – When low, a valid linear PCM audio stream is indicated. See

“Non-Audio Detection” on page 31. This pin is also used to select the serial port format (SFSEL1) at

reset.

96 kHz Sample Rate Detect (Output) - If the input sample rate is ≤ 48 kHz, outputs a “0”. Outputs a

“1” if the sample rate is ≥ 88.1 kHz. Otherwise the output is indeterminate. Also used to set the

Emphasis Audio Match feature at reset.

Receiver Channel Status Block (Output) -Indicates the beginning of a received channel status block.

RCBL goes high two frames after the reception of a Z preamble, remains high for 16 frames and then

returns low for the remainder of the block. RCBL changes on rising edges of RMCK. Also used to set

the serial audio port to master or slave at reset.

Channel Status Data (Output) - Outputs channel status data from the AES3 receiver, clocked by the

rising and falling edges of OLRCK. Also used to select the serial port format (SFSEL0) at reset.

User Data (Output) - Outputs user data from the AES3 receiver, clocked by the rising and falling

edges of OLRCK. Also used to select the frequency of RMCK to either 256*Fs or 128*Fs at reset.

DS578F3

17

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