CS8126 Просмотр технического описания (PDF) - Cherry semiconductor

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CS8126

5V, 750mA Low Dropout Linear Regulator with Delayed RESET

Cherry semiconductor 

VOUT

VRT(ON)

VRT(OFF)

VRH

RESET

(3)

VRL

Delay

VDC(HI)

VDC(LO)

VDH

RESET Circuit Waveform

(1)

(2)

tDelay

(2)

(1) = No Delay Capacitor

(2) = With Delay Capacitor

(3) = Max: RESET Voltage (1.0V)

VDIS

Circuit Description

The CS8126 RESET function, has hysteresis on both the

Reset and Delay comparators, a latching Delay capacitor

discharge circuit, and operates down to 1V.

The RESET circuit output is an open collector type with

ON and OFF parameters as specified. The RESET output

NPN transistor is controlled by the two circuits described

(see Block Diagram).

Low Voltage Inhibit Circuit

This circuit monitors output voltage, and when the output

voltage falls below VRT(OFF), causes the RESET output tran-

sistor to be in the ON (saturation) state. When the output

voltage rises above VRT(ON), this circuit permits the RESET

output transistor to go into the OFF state if allowed by

the RESET Delay circuit.

RESET Delay Circuit

This circuit provides a programmable (by external capaci-

tor) delay on the RESET output lead. The Delay lead pro-

vides source current to the external delay capacitor only

when the "Low Voltage Inhibit" circuit indicates that out-

put voltage is above VRT(ON). Otherwise, the Delay lead

sinks current to ground (used to discharge the delay

capacitor). The discharge current is latched ON when the

output voltage falls below VRT(OFF). The Delay capacitor is

fully discharged anytime the output voltage falls out of

regulation, even for a short period of time. This feature

ensures a controlled RESET pulse is generated following

detection of an error condition. The circuit allows

the RESET output transistor to go to the OFF (open) state

only when the voltage on the Delay lead is higher than

VDC(H1).

The Delay time for the RESET function is calculated from

the formula:

Delay time =

CDelay ´ VDelay Threshold

ICharge

Delay time = CDelay ´ 3.2 ´ 105

If CDelay = 0.1µF, Delay time (ms) = 32ms ± 50%: i.e. 16ms

to 48ms. The tolerance of the capacitor must be taken into

account to calculate the total variation in the delay time.

5

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