CS7666 Просмотр технического описания (PDF) - Cirrus Logic

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CS7666

Digital Color-Space Processor for CCD Cameras

Cirrus Logic 

CS7666

then sending a one-byte station address indicating

read to the CS7666. The data from register 19h is

then returned by the CS7666.

Byte Sequence WRITE Format Packet Detail

First Byte

Station Address of CS7666 with

LSB Set LOW

Second Byte Station Address of CS7666 with

LSB Set LOW

Third Byte

Slave Data Hold reg. address 19h

Table 13. Address Set for Slave Data Hold register in

Four-byte mode

Byte Sequence READ Format Packet Details

First Byte

CS7666 Station Address with LSB

set HIGH.

Second Byte Returned data from register 19h of

CS7666

Table 14. READ Format Packet.

Initializing Slave Devices on Secondary I2C

bus from an EPROM

An EPROM may be attached to the secondary I2C

bus for initialization purposes. Resetting the

CS7666 initiates a download of register values

from the EPROM into any of the slave devices on

the secondary I2C bus. The EPROM is assumed to

be at station address A0h. If during initialization,

the CS7666 does not receive an acknowledge bit

from the EPROM, all transactions with the

EPROM are aborted and the NODEV status bit is

set in status register at address 01h.

The data within the EPROM is formatted in three-

byte packets that represent the destination address,

register address, and data. After reading a packet,

the CS7666 initiates an I2C bus cycle using the first

byte as the device station address, the second byte

as the device register address, and the third byte as

the data being written to the device. If an acknowl-

edge is received from the target device, the CS7666

will fetch the next 3 bytes from the EPROM and re-

peat the process. The only exception being the

gamma table whose entire 256 bytes is transferred

in one I2C write cycle. This process will continue

until the total number of packets read equals the

value in the EEPROM count register (registers 1Ah

and 1Bh), a HALT command is executed, or no ac-

knowledge is received from the target device.

While the CS7666 is downloading from the

EPROM, the INITACT bit (register 01h bit3) is set

in the status register of CS7666. All attempts to

write to CS7666 registers by an external controller

will be ignored during this time.

Controlling the Configuration Process

The simplest configuration would consist of an

EPROM with one configuration file. In this case,

the first commands in the EPROM should write the

total number of packets in the EEPROM. This data

is written to the EEPROM count high and low byte

registers (registers 1Ah and 1Bh). Subsequent

bytes would contain all the necessary data to con-

figure the camera. This data will be read in a se-

quential fashion.

If, however, multiple configurations are desired,

the EEPROM may be programmed with multiple

sets of data, and the CS7666 programmed to select

one of 8 configurations. The CS7666 incorporates

3 commands to handle multiple configurations:

SKIP, JUMP, and HALT.

The SKIP command tells the CS7666 to skip to the

address within the EEPROM specified by the Con-

figuration Control registers (30h - 3Fh). The Con-

figuration Control registers are used in pairs to

provide a 11-bit EEPROM address. The Configura-

tion Index register determines which two of the 8

pairs will be used.

The Configuration Index Register is loaded auto-

matically after reset by the CS7666. The CS7666

will attempt a read cycle from the parallel I/O port

of a Crystal CS495X series video encoder or

SAA8574 I2C port expander from Philips Semi-

conductors. If the read cycle is successful, the Con-

figuration Index register will contain the state of

the lower 3 bits of the parallel I/O port. If both the

DS302PP1

19

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