CS7620 Просмотр технического описания (PDF) - Cirrus Logic

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CS7620

CCD Imager Analog Processor

Cirrus Logic 

CS7620

3.4.5 Vertical Timing Generator

The signals involved in the vertical timing genera-

tor are the vertical shift clocks V1 through V4 and

the storage clocks S1 through S4. The vertical tim-

ing generator generates the signals needed by the

CCD to shift charge vertically down into the hori-

zontal shift register. The chip is the timing master,

and it generates the signals needed by the horizon-

tal timing generator and other modules to operate.

The timing generator is controlled externally by

various signals; the falling edge of the input signal

EXPOSE sets the part into readout mode, and after

this edge, it generates the timing signals to output a

full frame, provided that RST and PWR_DN are

not active.

The mode register selects the CCD timing, and the

resolution mode to be generated. Please refer to

IBM-CCD datasheet for more info.

Mode value

Mode

000 IBM35CCD2PIX1 and IBM35CCDPIX13

CCD high resolution mode

001 IBM35CCD2PIX1 CCD low resolution

(viewfinder) mode

010-100 reserved

101 IBM35CCD13PIX CCD (2x2) low resolu-

tion (viewfinder) mode

110 IBM35CCD13PIX CCD (3x4) low resolu-

tion (viewfinder) mode

111 external timing used

Table 3. Different Resolution Operating Modes

The timing module’s functionality can be config-

ured through the use of registers. Note that before

entering a preview mode, all of the programmable

parameters must be set prior to this.

Shiftl_num is the number of lines in the shift buff-

er.

Tdv is the length of the minimum vertical timing

interval measured in pixel clocks.

Num_pixels is the number of pixels per line

Num_lines is the number of lines per frame.

V_polarity allows to switch the polarity of all the

vertical timing signals going to the CCD.

Blk_begin is the first black pixel in a line

Blk_end is the last black pixel in a line

Drk_rws_fst is the number of black lines to be

readout at the beginning of the frame

Drk_rws_lst is the number of black lines to be

readout at the end of the frame

3.4.6 Frame Timing

Figures 21 and 22 illustrates the frame timing for

the low and high resolution modes.

HSYNC is high during the active pixel area, and it

is low during vertical shift (horizontal and vertical

blanking periods).

RD_OUT is triggered by the falling edge of ex-

pose, it is delayed by the chip latency, and it

switches back high once the last pixel has been read

out of the CS7620. RD_OUT is low during the ac-

tive pixel areas and during the horizontal blanking

periods (vertical line shifts) and it goes high during

the vertical blanking period, between frames.

The dotted lines in Figures 21 and 22 correspond to

the vsync option which can be enabled by writing a

one to register vsync_md (register 25h bit 5). This

causes the RD_OUT signal to behave like a vertical

sync signal. It makes the signals HSYNC and

RD_OUT the same length at the beginning of a

new frame (see Figures 21 and 22).

3.5 Frequency Synthesizer

Since multiple clock phases and timing are re-

quired for the pixel rate clocks controlling the CCD

imager, the clock generator contains a PLL circuit

to generate the proper timing. “Frequency Synthe-

sizer Parameters” on page 6 shows the require-

ments for this PLL. The frequency of the input

clock may be set from 1 to 20X the pixel clk fre-

quency, in integer multiples. The frequency used is

DS301PP2

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