CDB6422 Просмотр технического описания (PDF) - Cirrus Logic

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CDB6422

Enhanced Full-Duplex Speakerphone IC

Cirrus Logic 

CS6422

4.1.4.3 Double-talk Attenuation ....................................................................... 36

4.1.4.4 Noise Guard ........................................................................................ 37

4.2 Circuit Design ................................................................................................................... 37

4.2.1 Interface Considerations ..................................................................................... 37

4.2.1.1 Analog Interface .................................................................................. 37

4.2.1.2 Microcontroller Interface ...................................................................... 37

4.2.2 Grounding Considerations .................................................................................. 38

4.2.3 Layout Considerations ........................................................................................ 38

4.3 System Design ................................................................................................................. 38

4.3.1 Gain Structure ..................................................................................................... 38

4.3.2 Testing Issues ..................................................................................................... 39

4.3.2.1 ERLE ................................................................................................... 39

4.3.2.2 Convergence Time .............................................................................. 40

4.3.2.3 Half-Duplex Switching ......................................................................... 40

5. PIN DESCRIPTIONS .............................................................................................................. 41

6. GLOSSARY ............................................................................................................................ 44

7. PACKAGE DIMENSIONS ....................................................................................................... 46

LIST OF FIGURES

Figure 1. CLKI Timing ................................................................................................................... 7

Figure 2. Reset Timing .................................................................................................................. 7

Figure 3. Microcontroller Interface Timing ..................................................................................... 7

Figure 4. Typical Connection Diagram (Microphone Preamplifier Enabled) ................................. 8

Figure 5. Typical Connection Diagram (Microphone Preamplifier Disabled) ................................ 8

Figure 6. Analog Interface ........................................................................................................... 10

Figure 7. Microcontroller Interface .............................................................................................. 12

Figure 8. Suggested Layout ........................................................................................................ 29

Figure 9. Ground Planes ............................................................................................................. 30

Figure 10. Simplified Acoustic Echo Canceller Block Diagram ................................................... 31

Figure 11. How the AGC works (TVol = +30 dB) ........................................................................ 35

LIST OF TABLES

Table 1. Full scale voltages for each gain stage ........................................................................... 11

Table 2. MCR Control Register Mapping ...................................................................................... 12

Table 3. Register 0 Bit Definitions................................................................................................. 13

Table 4. Register 1 Bit Definitions................................................................................................. 16

Table 5. Register 2 Bit Definitions................................................................................................. 18

Table 6. Register 3 Bit Definitions................................................................................................. 21

Table 7. Register 4 Bit Definitions................................................................................................. 23

Table 8. Register 5 Bit Definitions................................................................................................. 25

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DS295F1

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