CDB6422 Просмотр технического описания (PDF) - Cirrus Logic

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CDB6422

Enhanced Full-Duplex Speakerphone IC

Cirrus Logic 

CS6422

through the Microcontroller Interface. This gain

stage allows gains of 0 dB, 6 dB, 9.5 dB, and 12 dB

to be added prior to the ADC input. The default

gain stage setting is 0 dB.

The signal at APO should not exceed 2.5 Vpp at the

0 dB gain stage setting. If a different gain setting is

used, then the full-scale signal at APO must also

change. Table 1 shows full-scale voltages as mea-

sured at APO for the given programmable gain:

Gain Setting

Full-scale Voltage

0 dB

6 dB

9.5 dB

12 dB

2.5 Vpp

1.25 Vpp

0.84 Vpp

0.63 Vpp

Table 1. Full scale voltages for each gain stage

MB serves to provide decoupling for the internal

voltage reference, and must have a 0.1 µF and a

10 µF capacitor to ground for bypass. Noise on MB

will strongly influence the overall analog perfor-

mance of the CS6422.

The acoustic output, AO, should connect to a sin-

gle-pole low-pass RC network with a corner fre-

quency of 4 kHz, which will filter out-of-band

components. The full-scale voltage swing at AO is

3.1 Vpp maximum, 1 Vrms typical. AO is capable of

driving a load of 10 kΩ or more.

3.1.2 Network Interface

The pins NI (pin 17) and NO (pin 4) form the Net-

work Interface. The details of the Network Inter-

face are shown in Figure 6.

NI is the input from the telephone network into the

CS6422. The signal into NI must be low pass fil-

tered by a single-pole RC filter with a corner fre-

quency of 8 kHz.

RGain, a programmable analog gain stage accessi-

ble through the Microcontroller Interface, ampli-

fies signals received at NI. This gain stage allows a

gain of 0 dB, 6 dB, 9.5 dB, or 12 dB to be added

prior to the ADC input. The default gain stage set-

ting for the network side is 0 dB.

The signal at NI should not exceed 2.5 Vpp at the

0 dB gain stage setting. If another gain setting is se-

lected, then the full-scale signal at NI will change.

Table 1 shows full-scale voltages as measured at NI

for the given programmable gain.

The output to the telephone network side, NO,

should connect to a single pole RC network with a

corner frequency at 4 kHz, which will filter out-of-

band components. The maximum swing NO is ca-

pable of producing is 3.1 Vpp maximum, 1 Vrms

typical. NO is capable of driving a load of 10 kΩ or

more.

3.2 Microcontroller Interface

The registers and control functions of the CS6422

are accessible through the Microcontroller Inter-

face, which consists of three pins: DATA (pin 8),

STROBE (pin 7), and DRDY (pin 6). These inputs

can connect to the outputs of a microcontroller to

allow write-only access to the 16-bit Microcontrol-

ler Control Register (MCR).

3.2.1 Description

The Microcontroller Interface is implemented by a

serial shift register that is clocked by STROBE and

gated by DRDY. The microcontroller begins the

transaction by setting DRDY low while STROBE

is low. The most significant bit (MSB), Bit 15, of

the 16-bit data word should be presented to the

DATA pin and then STROBE should be brought

high to shift the data bit into the CS6422. STROBE

should be brought low again so it is ready to shift

the next bit into the shift register. The next data bit

should then be presented to the DATA pin ready to

be latched by the rising edge of STROBE. This pro-

cedure repeats for all sixteen bits as shown in Fig-

ure 7. After the last bit (Bit 0) has been shifted in,

DRDY should be brought high to indicate the con-

clusion of the transfer, and four or more extra

12

DS295F1

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