CS5102A Просмотр технического описания (PDF) - Cirrus Logic

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CS5102A

16-bit, 100 kSps / 20 kSps A/D Converters

Cirrus Logic 

CS5101A CS5102A

LIST OF FIGURES

Figure 1. Reset, Calibration, and Control Timing .......................................................................... 10

Figure 2. Serial Communication Timing ........................................................................................ 12

Figure 3. Coarse Charge Input Buffers & Charge Redistribution DAC.......................................... 15

Figure 4. Coarse/Fine Charge Control .......................................................................................... 18

Figure 5. Pipelined Data Transmission (PDT) Mode Timing ......................................................... 20

Figure 6. Register Burst Transmission (RBT) Mode Timing.......................................................... 21

Figure 7. Synchronous Self-clocking (SSC) Mode Timing ............................................................ 21

Figure 8. Free Run (FRN) Mode Timing........................................................................................ 21

Figure 9. CS5101A/CS5102A System Connection Diagram......................................................... 22

Figure 10. Power-up Reset Circuit ................................................................................................ 23

Figure 11. Reference Connections................................................................................................ 24

Figure 12. Charge Settling Time ................................................................................................... 24

Figure 13. CS5101A DNL Plot - Ambient Temperature at 25 °C .................................................. 27

Figure 14. CS5101A DNL Plot - Ambient Temperature at 138 °C ................................................ 27

Figure 15. CS5102A DNL Plot - Ambient Temperature at 25 °C .................................................. 27

Figure 16. CS5102A DNL Plot - Ambient Temperature at 138 °C ................................................ 27

Figure 17. CS5101A DNL Error Distribution.................................................................................. 28

Figure 18. CS5102A DNL Error Distribution.................................................................................. 28

Figure 19. CS5101A FFT (SSC Mode, 1-Channel)....................................................................... 29

Figure 20. CS5101A FFT (SSC Mode, 1-Channel)....................................................................... 29

Figure 21. CS5102A FFT (SSC Mode, 1-Channel)....................................................................... 29

Figure 22. CS5102A FFT (SSC Mode, 1-Channle)....................................................................... 29

Figure 23. CS5101A Histogram Plot of 8192 Conversion Inputs .................................................. 31

Figure 24. CS5102A Histogram Plot of 8192 Conversion Inputs .................................................. 31

Figure 25. Power Supply Rejection ............................................................................................... 32

Figure 26. CS5101A & CS5102A 28-pin PLCC Pinout ................................................................. 33

Figure 27. 28-Pin PLCC Mechanical Drawing............................................................................... 37

LIST OF TABLES

Table 1. Output Coding ................................................................................................................. 19

Table 2. Output Mode Control ....................................................................................................... 19

DS45F6

3

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