CMX625 Просмотр технического описания (PDF) - CML Microsystems Plc

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CMX625

ISDN TA POTS Interface

CML Microsystems Plc 

ISDN TA POTS Interface

CMX625

The CMX625 is programmed via the ‘MON1’ (Monitor Channel 1) channel in TE mode and the ‘Monitor’

channel in non-TE mode. The programming sequence consists of 3 consecutive Monitor bytes: the IOM-2

address, the CMX625 command and data byte. Before executing a command, the CMX625 compares the

received IOM-2 address byte with its own address. The MSB of the IOM-2 address is always a ‘1’ (see

section 1.5.2). A logical ‘1’ in the MSB of the CMX625 command represents a write operation and a

logical ‘0’ represents a read operation.

Structure for Register read/write operations:

IOM

R/W

Register Register Register Register

Command 0=Read

0

X

X

Address Address Address Address

Register 1=Write

A3

A2

A1

A0

Example 1: Program the CMX625 to generate interrupt requests for DTMF RX Status Change on bit 5 of

C/I channel, i.e. C/I1 Channel Output Control Code (2-0)=110. Set IOM-2 address to SA2-SA0=010 and

device select, DS=1.

MX MR

(DD) (DU)

11

01

00

10

01

10

01

10

11

01

00

10

01

10

01

10

11

11

DD

(hex)

FF

A8

A8

88

88

06

06

FF

FF

A8

A8

89

89

20

20

FF

FF

FF

MX MR

(DU) (DD)

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

DU

(hex)

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

Comment

Monitor Channel Idle State

Transmit IOM-2 Address

Acknowledge Address

Transmit Command (Write IOM-2 Control, $8)

Acknowledge Command/ Transmit IOM-2 Control Data

Acknowledge Data

End of Transmission

Transmit IOM-2 Address

Acknowledge Address

Transmit Command (Write Mask Register, $9)

Acknowledge Command/ Transmit IOM-2 Control Data

Acknowledge Data

End of Transmission

Idle

If the command is a register read then only the address and command bytes are sent. The CMX625 will

respond with an IOM-2 Register address byte followed by the read data. The IOM-2 Register address byte

consists of the Register address that is being read in the least significant 4 bits and the IOM-2 address

(less the device select bit) in the most significant 4 bits.

 2001 Consumer Microcircuits Limited

21

D/625/2

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