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CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

REVISION HISTORY

Version 1.0 - Initial version, generated March 1997.

Version 2.0 - Generated September 1997.

In addition to minor revisions, the following modifications have been made to the CL-PS7111 Data Book.

List of Revisions

Version

Section

Page

Revision Note

2.0 Features

1

Under ultra low power, the following bullet was added:

Average 45mW/66 mW in normal operation (2.7 V/3.3 V, 13 MHz/18.432 MHz).

2.0

Functional Block

Diagram

For the Sync. Serial Interface, the pin names ADCCLK, ADCIN, ADCOUT, and

SMPCLK replaced CLK, IN, and OUT.

1,19

For the Codec Interface, the pin names PCMCLK, PCMSYNC, PCMIN, and

PCMOUT replaced CLK, SYNC IN, OUT, and SMPCK.

2.0 3.7 State Control

24 New text was added.

2.0 4. Memory Map

43 This section was moved from Section 3.1 in version 1.0.

2.0

5. Register

Descriptions

This section was moved from Section 3.2 in version 1.0.

44 to 72 Bit numbers were added to the register descriptions. Register descriptions were

also reformatted and reorganized to aid users’ understanding.

2.0 Table 5-1

In the ‘R/W’ column, SYSFLG1 (8000.0140) and INTSR1 (8000.0240) were

45 changed from RD to R, and STFCLR (8000.05C0) through STDBY (8000.0840)

were changed from WR to W.

2.0 5.9 SYSFLG1

51 A description for the SSIBUSY bit was added.

2.0 5.38 SYSFLG1

71

The following text was added to the description of the CODECEN bit:

This bit must always be set to ‘1’.

March 1997

CIRRUS LOGIC CONFIDENTIAL

ADVANCE DATA BOOK v2.0

REVISION HISTORY

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