CL-PS7111-VC-A Просмотр технического описания (PDF) - Cirrus Logic
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CL-PS7111-VC-A Datasheet PDF : 105 Pages
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CL-PS7111
Low-Power System-on-a-Chip
3.1 Main Functional Blocks
The CL-PS7111 is built around the ARM710a processor core. For a more detailed description of the
ARM710a, refer to the ARM710a Macrocell Data Sheet (http://www.arm.com/).
The main functional blocks in CL-PS7111 are:
q ARM7 CPU core
q 8 Kbytes of unified instruction and data cache, a four-way set-associative
q Memory management unit (MMU)
q Two 16-bit general-purpose counters
q A 32-bit realtime clock and comparator
q On-chip boot ROM programmed with serial boot load sequence
q Advanced system state control and power management
q Direct interface to two CL-PS6700 PCMCIA controllers
q Expansion and ROM interface for four, five, or six 256-Mbyte expansion segments with independent wait
state control
q DRAM controller supporting Fast Page mode, self-refresh in Standby mode, and both 16-bit and 32-bit-wide
memory
q Programmable LCD controller with 1-, 4-, or 16-level grayscaler
q 2 Kbytes of SRAM for a small LCD frame buffer
q IrDA SIR protocol controller, capable of speeds up to 115.2 kbps
q Two full-duplex 16C550 style UARTs with two 16-byte FIFOs
q Main oscillator with PLL (phase locked loop) to generate the system clock of 18.432 MHz from a 3.6864-MHz
crystal
q Optional external 13-MHz clock input
q A low-power 32.768-kHz oscillator
q Interrupt and fast interrupt controller
q 27 bits of general-purpose I/Os
q Two DC-to-DC converter interfaces
q One synchronous serial interface for Microwire® or SPI® peripherals (such as ADCs)
q Telephony codec interface with 16-byte FIFOs for transmit and receive
q Programmable frame buffer start address, allowing a system to be built using only external or internal SRAMs
for memory, eliminating any need for DRAMs
q Pin test and device-isolation test logic
q External tracing support for debug
18
FUNCTIONAL DESCRIPTION
September 1997
PRELIMINARY DATA BOOK v2.0
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