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CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

3.2 System Maximization

A maximum-configured system using the CL-PS7111 is shown in Figure 3-3. This system assumes all

DRAMs and ROMs are 16-bit-wide devices. Watch-dog-timer tick rate is 1 Hz (in 13-MHz and 18.432-MHz

modes). This 1-Hz clock is generated by a divider chain that divides the 64-Hz clock. The LSB of the

RTCDIV field (SYSFLG[21:16]) provides the 1-Hz clock.

NOTE: The keyboard can be connected to more GPIO bits than illustrated to allow more than 64 keys. These extra

pins, however, will not be wired into the WAKEUP pin functionality.

OSCILLATOR

PC CARD

SOCETS

CL-PS6700

PC CARD

CONTROLLER

× 16

DRAM

× 16

DRAM

× 16

DRAM

× 16

DRAM

× 16

FLASH

× 16

FLASH

× 16

ROM

× 16

ROM

EXTERNAL MEMORY

MAPPED EXPANSION

BUFFERS

ADDITIONAL I/O

BUFFERS

AND

LATCHES

CL-PS7111

NCS[4]

PB0

EXPCLK

DD[3:0]

CL1

CL2

FRM

M

D[31:0]

A[27:0]

NMOE

WRITE

COL[7:0]

PA[7:0]

PB[7:0]

PD[7:0]

NRAS[1]

NRAS[0]

NCAS[0]

NCAS[1]

NCAS[2]

NCAS[3]

NCS[0]

NCS[1]

PE[2:0]

NPOR

NPWRFL

BATOK

NEXTPWR

NBATCHG

RUN

WAKEUP

DRIVE[1:0]

FB[1:0]

PCMSYNC

PCMOUT

PCMCLK

PCMIN

CS[n]

WORD

LEDDRV

PHDIN

NCS[2]

NCS[3]

RXD1/2

TXD1/2

DSR

CTS

DCD

ADCCLK

NADCCS

ADCOUT

ADCIN

SMPCLK

LCD MODULE

KEYBOARD

POWER

SUPPLY UNIT

AND

COMPARATORS

DC

INPUT

BATTERY

DC-TO-DC

CONVERTERS

CODEC

IR LED AND

PHOTODIODE

2× RS-232

TRANSEIVER

ADC

DIGITIZER

Figure 3-3. A Maximized CL-PS7111–Based System

20

FUNCTIONAL DESCRIPTION

September 1997

PRELIMINARY DATA BOOK v2.0

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