CS4361 Просмотр технического описания (PDF) - Cirrus Logic

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CS4361

20-Pin, 24-Bit, 192 kHz, 6-Channel D/A Converter

Cirrus Logic 

Confidential Draft

2/12/08

SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE

CS4361

Parameters

Symbol

MCLK Frequency

MCLK Duty Cycle

Input Sample Rate All MCLK/LRCK ratios combined Fs

(Note 11)

256x, 384x, 1024x

256x, 384x

512x, 768x

1152x

128x, 192x

64x, 96x

128x, 192x

External SCLK Mode

LRCK Duty Cycle (External SCLK only)

SCLK Pulse Width Low

SCLK Pulse Width High

SCLK Duty Cycle

tsclkl

tsclkh

SCLK rising to LRCK edge delay

SCLK rising to LRCK edge setup time

SDIN valid to SCLK rising setup time

SCLK rising to SDIN hold time

Internal SCLK Mode

tslrd

tslrs

tsdlrs

tsdh

LRCK Duty Cycle (Internal SCLK only) (Note 12)

SCLK Period

tsclkw

(Note 13)

SCLK rising to LRCK edge

tsclkr

Min

0.512

45

2

2

84

42

30

50

100

168

45

20

20

45

20

20

20

20

-

-----1---0---9-----

SCLK

-

SDIN valid to SCLK rising setup time

tsdlrs

(---5---1-1---20---)-9--F----s- + 10

SCLK rising to SDIN hold time

tsdh

MCLK / LRCK =1152, 1024, 512, 256, 128, or 64

SCLK rising to SDIN hold time

tsdh

MCLK / LRCK = 768, 384, 192, or 96

(---5---1-1---20---)-9--F----s- + 15

-------1---0----9------- + 15

( 384 ) F s

Typ

-

-

50

-

-

50

-

-

-

-

50

-

t---s---c---l--k---w---

2

-

-

-

Max

Units

50

MHz

55

%

216

kHz

54

kHz

134

kHz

67

kHz

34

kHz

108

kHz

216

kHz

216

kHz

55

%

-

ns

-

ns

55

%

-

ns

-

ns

-

ns

-

ns

-

%

-

ns

-

µs

-

ns

-

ns

-

ns

11. Not all sample rates are supported for all clock ratios. See table “Common Clock Frequencies” on

page 12 for supported ratios and frequencies.

12. In Internal SCLK Mode, the duty cycle must be 50% ± 1/2 MCLK period.

13. The SCLK / LRCK ratio may be either 32, 48, 64, or 72. This ratio depends on data format and

MCLK/LRCK ratio. (See Figures 7-10)

9

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