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VP306SCGGP1N

Satellite Channel Decoder

Mitel Networks 

VP305/6

DRAFT - PRELIMINARY DATA

The comparison frequency, Fcomp =

Fcrystal

CR_RP * 1024

MHz.

The upper and lower sweep boundaries are set by the CR_USWL and CR_LSWL respectively.

These registers actually set the division ratios for dividing the I/Q down converter VCO frequency.

The value programmed must take account of any fixed prescaler in the I/Q down converter, for the

SL1710 this is divide by 32.

The comparison frequency, Fcomp =

Fvco

32 * CR_U/LSWL

MHz.

Therefore,

Fcrystal

CR_RP * 1024

=

Fvco

32 * CR_U/LSWL

Therefore, Fcrystal * 32 * CR_U/LSWL = Fvco * CR_RP * 1024

Therefore,

Fvco

Fcrystal

=

32 * CR_U/LSWL

CR_RP * 1024

The upper and lower sweep limits can be expressed in terms of the above equations together with

two further terms including the delta variation in frequency.

Let the delta variation in frequency = ± δF.

Then the frequency limits are Fvco + δF and Fvco - δF.

Therefore,

CR_USWL =

(Fvco + δF) * CR_RP * 1024

Fcrystal * 32

and

CR_LSWL =

(Fvco - δF) * CR_RP * 1024

Fcrystal * 32

When the AFC circuit achieves lock, as indicated by the CR_FLOCK bit in the STATUS register

going high, the scaled carrier frequency can be read from the CR_VCOF U & L registers.

The actual carrier frequency is found from the following formula:

Fvco

=

32 * Fcrystal

CR_RP * 1024

*

CR_VCOF

MHz

see page 30.

1.2.6. Symbol synchronisation and tracking

The VP216/7 local oscillator frequency must be programmed to be at least twice the required

symbol rate and is maintained by a Phase Locked Loop on the VP305/6. The ADC sample

frequency should be adjusted by setting the SYM_NF and SYM_RP division ratios to match the

decimation rate chosen. The VP216/7 voltage controlled oscillator (VCO) frequency is connected

to the VP305/6 SYS_CLK input and then to the SYM_NF divider. The output from the SYM_NF

divider is compared with the crystal oscillator frequency divided by the SYM_RP division ratio. A

push-pull feedback signal (SYM_VCO) is output to an active filter to complete the loop and control

the VP216/7 VCO, see Fig. 3 on page 9.

The duplication or disclosure of data contained on this sheet is subject to the restrictions

on the title page of this document.

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