IDT72V3650L10PFI Просмотр технического описания (PDF) - Integrated Device Technology
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IDT72V3650L10PFI Datasheet PDF : 36 Pages
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IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RCLK
tENS
REN
Q0 - Qn
Wx
WCLK
WEN
RT
1
2
Wx+1
tRTS
tENS
tA
tA
W1
tSKEW2
1
2
tENH
3
tA
W2 (4)
4
tA
W3 (4)
5
tENH
tA
W4 (4)
W5
OR
tPAES
PAE
tHF
HF
PAF
tPAFS
4667 drw 19
NOTES:
1. If the part is empty at the point of Retransmit, the output ready flag (OR) will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680, 32,769 for the IDT72V3690, 65,537
for the IDT72V36100 and 131,073 for the IDT72V36110.
3. OE = LOW.
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during MRS.
Figure 14. Zero Latency Retransmit Timing (FWFT Mode)
WCLK
SEN
LD
SI
t ENS
tLDS
tDS
BIT 0
tENH
tLDH
EMPTY OFFSET
(1)
BIT X
BIT 0
FULL OFFSET
tENH
tLDH
tDH
(1)
BIT X
4667 drw 20
NOTE:
1. X = 9 for the IDT72V3640, X = 10 for the IDT72V3650, X = 11 for the IDT72V3660, X = 12 for the IDT72V3670, X = 13 for the IDT72V3680, X = 14 for the IDT72V3690, X = 15 for
the IDT72V36100 and X = 16 for the IDT72V36110.
Figure 15. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
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