IDT72V3650L10PFI Просмотр технического описания (PDF) - Integrated Device Technology

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IDT72V3650L10PFI

3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO

Integrated Device Technology 

IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO

1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

RCLK

tENS

REN

Q0 - Qn

Wx

tENH

tRTS

Wx+1

tSKEW2

1

2

tENS

tA

tA

(4)

W1

3

tA

W2 (4)

4

tENH

tA

W3 (4)

W4

WCLK

WEN

RT

OR

PAE

tRTS

tENS

1

tENH

tREF

2

tREF

tHF

tPAES

HF

tPAFS

PAF

4667 drw 17

NOTES:

1. Retransmit setup is complete after OR returns LOW.

2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.

D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680, 32,769 for the IDT72V3690, 65,537

for the IDT72V36100 and 131,073 for the IDT72V36110.

3. OE = LOW.

4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.

5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.

6. RM is set HIGH during MRS.

Figure 12. Retransmit Timing (FWFT Mode)

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