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IDT72V3670L10PFI

3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO

Integrated Device Technology 

IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO

1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36

BYTE ORDER ON INPUT PORT:

D35-D27

A

D26-D18

B

D17-D9

C

D8-D0

D

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

Write to FIFO

BYTE ORDER ON OUTPUT PORT:

BE BM IW OW

XLL L

BE BM IW OW

LH L

L

BE BM IW OW

HH L L

BE BM IW OW

LH L H

BE BM IW OW

HH L H

Q35-Q27

A

Q26-Q18

B

Q17-Q9

C

(a) x36 INPUT to x36 OUTPUT

Q8-Q0

D

Read from FIFO

Q35-Q27

Q26-Q18

Q17-Q9

A

Q8-Q0

B

Q35-Q27

Q26-Q18

Q17-Q9

C

Q8-Q0

D

(b) x36 INPUT to x18 OUTPUT - BIG-ENDIAN

Q35-Q27

Q26-Q18

Q17-Q9

C

Q8-Q0

D

1st: Read from FIFO

2nd: Read from FIFO

1st: Read from FIFO

Q35-Q27

Q26-Q18

Q17-Q9

A

Q8-Q0

B

(c) x36 INPUT to x18 OUTPUT - LITTLE-ENDIAN

Q35-Q27

Q26-Q18

Q17-Q9

Q8-Q0

A

2nd: Read from FIFO

1st: Read from FIFO

Q35-Q27

Q26-Q18

Q17-Q9

Q8-Q0

B

2nd: Read from FIFO

Q35-Q27

Q26-Q18

Q17-Q9

Q8-Q0

C

3rd: Read from FIFO

Q35-Q27

Q26-Q18

Q17-Q9

Q8-Q0

D

(d) x36 INPUT to x9 OUTPUT - BIG-ENDIAN

Q35-Q27

Q26-Q18

Q17-Q9

Q8-Q0

D

4th: Read from FIFO

1st: Read from FIFO

Q35-Q27

Q26-Q18

Q17-Q9

Q35-Q27

Q26-Q18

Q17-Q9

Q8-Q0

C

2nd: Read from FIFO

Q8-Q0

B

3rd: Read from FIFO

Q35-Q27

Q26-Q18

Q17-Q9

Q8-Q0

A

(e) x36 INPUT to x9 OUTPUT - LITTLE-ENDIAN

Figure 4. Bus-Matching Byte Arrangement

20

4th: Read from FIFO

4667 drw 08

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