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IDT72V3670L10PFI

3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO

Integrated Device Technology 

IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO

1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

after a reset (either MRS or PRS), FF will go LOW after D writes to the FIFO

(D = 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the

IDT72V3660, 8,192 for the IDT72V3670, 16,384 for the IDT72V3680, 32,768

for the IDT72V3690, 65,536 for the IDT72V36100 and 131,072 for the

IDT72V36110). See Figure 7, Write Cycle and Full Flag Timing (IDT Standard

Mode), for the relevant timing information.

In FWFT mode, the Input Ready (IR) function is selected. IR goes LOW

when memory space is available for writing in data. When there is no longer

any free space left, IR goes HIGH, inhibiting further write operations. If no reads

are performed after a reset (either MRS or PRS), IR will go HIGH after D writes

to the FIFO (D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097

for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680,

32,769 for the IDT72V3690, 65,537 for the IDT72V36100 and 131,073 for the

IDT72V36110). See Figure 9, Write Timing (FWFT Mode), for the relevant

timing information.

The IR status not only measures the contents of the FIFO memory, but also

counts the presence of a word in the output register. Thus, in FWFT mode, the

total number of writes necessary to deassert IR is one greater than needed to

assert FF in IDT Standard mode.

FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are

double register-buffered outputs.

EMPTY FLAG ( EF/OR )

This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (EF)

function is selected. When the FIFO is empty, EF will go LOW, inhibiting further

read operations. When EF is HIGH, the FIFO is not empty. See Figure 8, Read

Cycle, Empty Flag and First Word Latency Timing (IDT Standard Mode), for

the relevant timing information.

In FWFT mode, the Output Ready (OR) function is selected. OR goes LOW

at the same time that the first word written to an empty FIFO appears valid on

the outputs. OR stays LOW after the RCLK LOW to HIGH transition that shifts

the last word from the FIFO memory to the outputs. OR goes HIGH only with

a true read (RCLK with REN = LOW). The previous data stays at the outputs,

indicating the last word was read. Further data reads are inhibited until OR goes

LOW again. See Figure 10, Read Timing (FWFT Mode), for the relevant timing

information.

EF/OR is synchronous and updated on the rising edge of RCLK.

In IDT Standard mode, EF is a double register-buffered output. In FWFT

mode, OR is a triple register-buffered output.

PROGRAMMABLE ALMOST-FULL FLAG ( PAF )

The Programmable Almost-Full flag (PAF) will go LOW when the FIFO

reaches the almost-full condition. In IDT Standard mode, if no reads are

performed after reset (MRS), PAF will go LOW after (D - m) words are written

to the FIFO. The PAF will go LOW after (1,024-m) writes for the IDT72V3640,

(2,048-m) writes for the IDT72V3650, (4,096-m) writes for the IDT72V3660,

(8,192-m) writes for the IDT72V3670, (16,384-m) writes for the IDT72V3680,

(32,768-m) writes for the IDT72V3690, (65,536-m) writes for the IDT72V36100

and (131,072-m) writes for the IDT72V36110. The offset “m” is the full offset

value. The default setting for this value is stated in the footnote of Table 1.

In FWFT mode, the PAF will go LOW after (1,025-m) writes for the

IDT72V3640, (2,049-m) writes for the IDT72V3650, (4,097-m) writes for the

IDT72V3660 and (8,193-m) writes for the IDT72V3670, (16,385-m) writes for

the IDT72V3680, (32,769-m) writes for the IDT72V3690, (65,537-m) writes for

the IDT72V36100 and (131,073-m) writes for the IDT72V36110, where m is

the full offset value. The default setting for this value is stated in Table 2.

See Figure 18, Synchronous Programmable Almost-Full Flag Timing (IDT

Standard and FWFT Mode), for the relevant timing information.

If asynchronous PAF configuration is selected, the PAF is asserted LOW

on the LOW-to-HIGH transition of the Write Clock (WCLK). PAF is reset to HIGH

on the LOW-to-HIGH transition of the Read Clock (RCLK). If synchronous PAF

configuration is selected, the PAF is updated on the rising edge of WCLK. See

Figure 20, Asynchronous Almost-Full Flag Timing (IDT Standard and FWFT

Mode).

PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)

The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO

reaches the almost-empty condition. In IDT Standard mode, PAE will go LOW

when there are n words or less in the FIFO. The offset “n” is the empty offset

value. The default setting for this value is stated in the footnote of Table 1.

In FWFT mode, the PAE will go LOW when there are n+1 words or less

in the FIFO. The default setting for this value is stated in Table 2.

See Figure 19, Synchronous Programmable Almost-Empty Flag Timing

(IDT Standard and FWFT Mode), for the relevant timing information.

If asynchronous PAE configuration is selected, the PAE is asserted LOW

on the LOW-to-HIGH transition of the Read Clock (RCLK). PAE is reset to HIGH

on the LOW-to-HIGH transition of the Write Clock (WCLK). If synchronous PAE

configuration is selected, the PAE is updated on the rising edge of RCLK. See

Figure 21, Asynchronous Programmable Almost-Empty Flag Timing (IDT

Standard and FWFT Mode).

HALF-FULL FLAG ( HF )

This output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO

beyond half-full sets HF LOW. The flag remains LOW until the difference between

the write and read pointers becomes less than or equal to half of the total depth

of the device; the rising RCLK edge that accomplishes this condition sets HF

HIGH.

In IDT Standard mode, if no reads are performed after reset (MRS or PRS),

HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 1,024 for the

IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660, 8,192

for the IDT72V3670, 16,384 for the IDT72V3680, 32,768 for the IDT72V3690,

65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.

In FWFT mode, if no reads are performed after reset (MRS or PRS), HF

will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 1,025 for the

IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for

the IDT72V3670, 16,385 for the IDT72V3680, 32,769 for the IDT72V3690,

65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.

See Figure 22, Half-Full Flag Timing (IDT Standard and FWFT Modes),

for the relevant timing information. Because HF is updated by both RCLK and

WCLK, it is considered asynchronous.

DATA OUTPUTS (Q0-Qn)

(Q0-Q35) are data outputs for 36-bit wide data, (Q0 - Q17) are data outputs

for 18-bit wide data or (Q0-Q8) are data outputs for 9-bit wide data.

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