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IDT72V3660L15PFI

3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO

Integrated Device Technology 

IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO

1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting

further write operations. Upon the completion of a valid read cycle, IR will go

LOW allowing a write to occur. The IR flag is updated by two WCLK cycles +

tSKEW after the valid RCLK cycle.

WEN is ignored when the FIFO is full in either FWFT or IDT Standard mode.

READ CLOCK (RCLK)

A read cycle is initiated on the rising edge of the RCLK input. Data can be

read on the outputs, on the rising edge of the RCLK input. It is permissible to

stop the RCLK. Note that while RCLK is idle, the EF/OR, PAE and HF flags will

not be updated. (Note that RCLK is only capable of updating the HF flag to

HIGH.) The Write and Read Clocks can be independent or coincident.

READ ENABLE ( REN )

When Read Enable is LOW, data is loaded from the RAM array into the output

register on the rising edge of every RCLK cycle if the device is not empty.

When the REN input is HIGH, the output register holds the previous data

and no new data is loaded into the output register. The data outputs Q0-Qn

maintain the previous data value.

In the IDT Standard mode, every word accessed at Qn, including the first

word written to an empty FIFO, must be requested using REN. When the last

word has been read from the FIFO, the Empty Flag (EF) will go LOW, inhibiting

further read operations. REN is ignored when the FIFO is empty. Once a write

is performed, EF will go HIGH allowing a read to occur. The EF flag is updated

by two RCLK cycles + tSKEW after the valid WCLK cycle.

In the FWFT mode, the first word written to an empty FIFO automatically goes

to the outputs Qn, on the third valid LOW-to-HIGH transition of RCLK + tSKEW

after the first write. REN does not need to be asserted LOW. In order to access

all other words, a read must be executed using REN. The RCLK LOW-to-HIGH

transition after the last word has been read from the FIFO, Output Ready (OR)

will go HIGH with a true read (RCLK with REN = LOW), inhibiting further read

operations. REN is ignored when the FIFO is empty.

SERIAL ENABLE ( SEN )

The SEN input is an enable used only for serial programming of the offset

registers. The serial programming method must be selected during Master

Reset. SEN is always used in conjunction with LD. When these lines are both

LOW, data at the SI input can be loaded into the program register one bit for each

LOW-to-HIGH transition of WCLK.

When SEN is HIGH, the programmable registers retains the previous

settings and no offsets are loaded. SEN functions the same way in both IDT

Standard and FWFT modes.

OUTPUT ENABLE ( OE )

When Output Enable is enabled (LOW), the parallel output buffers receive

data from the output register. When OE is HIGH, the output data bus (Qn) goes

into a high impedance state.

LOAD ( LD )

This is a dual purpose pin. During Master Reset, the state of the LD input,

along with FSEL0 and FSEL1, determines one of eight default offset values for

the PAE and PAF flags, along with the method by which these offset registers

can be programmed, parallel or serial (see Table 2). After Master Reset, LD

enables write operations to and read operations from the offset registers. Only

the offset loading method currently selected can be used to write to the registers.

Offset registers can be read only in parallel.

After Master Reset, the LD pin is used to activate the programming process

of the flag offset values PAE and PAF. Pulling LD LOW will begin a serial loading

or parallel load or read of these offset values.

BUS-MATCHING (BM, IW, OW)

The pins BM, IW and OW are used to define the input and output bus widths.

During Master Reset, the state of these pins is used to configure the device bus

sizes. See Table 1 for control settings. All flags will operate on the word/byte

size boundary as defined by the selection of bus width. See Figure 4 for Bus-

Matching Byte Arrangement.

BIG-ENDIAN/LITTLE-ENDIAN ( BE )

During Master Reset, a LOW on BE will select Big-Endian operation. A

HIGH on BE during Master Reset will select Little-Endian format. This function

is useful when the following input to output bus widths are implemented: x36 to

x18, x36 to x9, x18 to x36 and x9 to x36. If Big-Endian mode is selected, then

the most significant byte (word) of the long word written into the FIFO will be read

out of the FIFO first, followed by the least significant byte. If Little-Endian format

is selected, then the least significant byte of the long word written into the FIFO

will be read out first, followed by the most significant byte. The mode desired is

configured during master reset by the state of the Big-Endian (BE) pin. See

Figure 4 for Bus-Matching Byte Arrangement.

PROGRAMMABLE FLAG MODE (PFM)

During Master Reset, a LOW on PFM will select Asynchronous Program-

mable flag timing mode. A HIGH on PFM will select Synchronous Programmable

flag timing mode. If asynchronous PAF/PAE configuration is selected (PFM,

LOW during MRS), the PAE is asserted LOW on the LOW-to-HIGH transition

of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of WCLK.

Similarly, the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and

PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK.

If synchronous PAE/PAF configuration is selected (PFM, HIGH during

MRS) , the PAE is asserted and updated on the rising edge of RCLK only and

not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK

only and not RCLK. The mode desired is configured during master reset by the

state of the Programmable Flag Mode (PFM) pin.

INTERSPERSED PARITY (IP)

During Master Reset, a LOW on IP will select Non-Interspersed Parity mode.

A HIGH will select Interspersed Parity mode. The IP bit function allows the user

to select the parity bit in the word loaded into the parallel port (D0-Dn) when

programming the flag offsets. If Interspersed Parity mode is selected, then the

FIFO will assume that the parity bits are located in bit position D8, D17, D26 and

D35 during the parallel programming of the flag offsets. If Non-Interspersed

Parity mode is selected, then D8, D17 and D28 are is assumed to be valid bits

and D32, D33, D34 and D35 are ignored. IP mode is selected during Master

Reset by the state of the IP input pin. Interspersed Parity control only has an

effect during parallel programming of the offset registers. It does not effect the data

written to and read from the FIFO.

OUTPUTS:

FULL FLAG ( FF/IR )

This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF) function

is selected. When the FIFO is full, FF will go LOW, inhibiting further write

operations. When FF is HIGH, the FIFO is not full. If no reads are performed

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