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IDT72V3660L15PFI

3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO

Integrated Device Technology 

IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO

1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36

BYTE ORDER ON INPUT PORT:

D35-D27

D26-D18

D17-D9

D8-D0

A

B

D35-D27

D26-D18

D17-D9

C

D8-D0

D

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

1st: Write to FIFO

2nd: Write to FIFO

BYTE ORDER ON OUTPUT PORT:

BE BM IW OW

LH H L

Q35-Q27 Q26-Q18

Q17-Q9

Q8-Q0

A

B

C

D

(a) x18 INPUT to x36 OUTPUT - BIG-ENDIAN

Read from FIFO

BE BM IW OW

HH H L

Q35-Q27

C

Q26-Q18

D

Q17-Q9

A

Q8-Q0

B

(b) x18 INPUT to x36 OUTPUT - LITTLE-ENDIAN

Read from FIFO

BYTE ORDER ON INPUT PORT:

D35-D27

D26-D18

D17-D9

D35-D27

D26-D18

D17-D9

D35-D27

D26-D18

D17-D9

D35-D27

D26-D18

D17-D9

D8-D0

A

D8-D0

B

D8-D0

C

D8-D0

D

1st: Write to FIFO

2nd: Write to FIFO

3rd: Write to FIFO

4th: Write to FIFO

BYTE ORDER ON OUTPUT PORT:

BE BM IW OW

LH H H

Q35-Q27

Q26-Q18

Q17-Q9

Q8-Q0

A

B

C

D

(a) x9 INPUT to x36 OUTPUT - BIG-ENDIAN

Read from FIFO

BE BM IW OW

HH H H

Q35-Q27

Q26-Q18

Q17-Q9

Q8-Q0

D

C

B

A

(b) x9 INPUT to x36 OUTPUT - LITTLE-ENDIAN

Read from FIFO

4667 drw 09

Figure 4. Bus-Matching Byte Arrangement (Continued)

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