IDT72V01L35J(1996) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT72V01L35J
(Rev.:1996)

3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9

Integrated Device Technology 

IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO

512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9

COMMERCIAL TEMPERATURE RANGE

W

t WEF

EF

t RPE

R

Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse

2679 drw 09

R

t RFF

FF

t WPF

W

Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse

2679 drw 10

W

R

HALF-FULL OR LESS

t WHF

HF

MORE THAN HALF-FULL

2678 drw 11

Figure 9. Half-Full Flag Timing

t RHF

HALF-FULL OR LESS

WRITE TO

LAST PHYSICAL

LOCATION

W

R

t XOL

t XOH

READ FROM

LAST PHYSICAL

LOCATION

t XOL

t XOH

XO

Figure 10. Expansion Out

2679 drw 12

5.08

8

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