IDT72V01L35J(1996) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT72V01L35J
(Rev.:1996)

3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9

Integrated Device Technology 

IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO

512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9

(HALF–FULL FLAG) (HF)

WRITE (W)

9

DATA IN (D)

FULL FLAG (FF)

RESET (RS)

IDT

9

72V01

72V02

72V03

72V04

COMMERCIAL TEMPERATURE RANGE

READ (R)

DATA OUT (Q)

EMPTY FLAG (EF)

RETRANSMIT (RT )

EXPANSION IN (XI)

Figure 12. Block Diagram of Single 1024 x 9 FIFO

2679 drw 14

18 9

DATA IN (D)

WRITE (W)

FULL FLAG (FF)

RESET (RS)

HF

IDT

72V01

72V02

72V03

72V04

9

9

HF

IDT

72V01

72V02

72V03

72V04

9

READ (R)

EMPTY FLAG (EF)

RETRANSMIT (RT )

XI

XI

18

DATA OUT (Q)

Figure 13. Block Diagram of 1024 x 18 FIFO Memory Used in Width Expansion Mode

2679 drw 15

TABLE I—RESET AND RETRANSMIT

Single Device Configuration/Width Expansion Mode

Mode

Reset

Retransmit

Read/Write

Inputs

RS

RT

XI

0

X

0

1

0

0

1

1

0

NOTE:

1. Pointer will increment if flag is High.

Internal Status

Read Pointer

Write Pointer

Location Zero

Location Zero

Location Zero

Increment(1)

Unchanged

Increment(1)

Outputs

EF

FF

0

1

X

X

X

X

HF

1

X

X

2679 tbl 09

TABLE II—RESET AND FIRST LOAD TRUTH TABLE

Depth Expansion/Compound Expansion Mode

Mode

Inputs

Internal Status

RS

FL

XI

Read Pointer

Write Pointer

Reset First Device

0

0

(1)

Location Zero

Location Zero

Reset All Other Devices

0

1

(1)

Location Zero

Location Zero

Read/Write

1

X

(1)

X

X

Outputs

EF

FF

0

1

0

1

X

X

NOTE:

2679 tbl 10

1. XI is connected to XO of previous device. See Figure 14. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Flag Full Output,

XI = Expansion Input, HF = Half-Full Flag Output

5.08

10

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