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IDT74FCT3907SO

3.3V PENTIUM™ CLOCK SYNTHESIZER

Integrated Device Technology 

IDT74FCT3907

3.3V PC CLOCK SYNTHESIZER

COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

74FCT3907

66.66MHz

60MHz

50MHz

Symbol

tCPU

CPUCLK Period

Parameter

Condition(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit

TBD

15 — 16.7 — 20 — ns

tCPUH

tCPUL

CPUCLK HIGH Time(3)

CPUCLK LOW Time(4)

4

—

4

—

4

— ns

4

—

4

—

4

— ns

tR1, tF1 CPUCLK Rise, Fall Times (Between 0.4V & 2.4V)

0.8 2.0 0.8 2.0 0.8 2.0 ns

tSK1(o) CPUCLK Output Skew

— 250 — 250 — 250 ps

tSK1(p) CPUCLK Pulse Skew

—

—

—

ps

|tPLH-tPHL|

tPCI

PCICLK Period

30 — 33.3 — 40 — ns

tPCIH PCICLK HIGH Time

12 — 13.3 — 16 — ns

tPCIL

PCICLK LOW Time

12 — 13.3 — 16 — ns

tR2, tF2 PCICLK Rise, Fall Time (Between 0.4V & 2.4V)

0.5 2.0 0.5 2.0 0.5 2.0 ns

tSK2(o) PCICLK Output Skew

— 500 — 500 — 500 ps

tSK2(p) PCICLK Pulse Skew

—

—

—

ps

|tPLH-tPHL|

tSK3(o) CPUCLK to PCICLK Output Delay

1.0 5.0 1.0 5.0 1.0 5.0 ns

tPS

CPUCLK, PCICLK Period Stability

— 250 — 250 — 250 ps

tCLOCK CPUCLK Lock Time

—

2

—

2

—

2 ms

tPLOCK PCICLK Lock Time

—

3

—

3

—

3 ms

tPZL

Output Enable Time OE to KBCLK,

tPZH

FDCLK, REFCLK, CPUCLK, PCICLK (Test Mode)

tPLZ

Output Disable Time OE to KBCLK,

tPHZ

FDCLK, REFCLK, CPUCLK, PCICLK (Test Mode)

NOTES:

1. See test circuit and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

1.5 8.0 1.5 8.0 1.5 8.0 ns

1.5 8.0 1.5 8.0 1.5 8.0 ns

3245 tbl 09

9.10

5

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