BU4015B Просмотр технического описания (PDF) - ROHM Semiconductor
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BU4015B Datasheet PDF : 18 Pages
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BU4015B,BU4015BF,BU4021B,BU4021BF,
BU4094BC,BU4094BCF,BU4094BCFV,BU4538B,BU4028B
Technical Note
Block diagram
SERIAL IN
CLOCK
8 STAGE
SHIFT REGISTER
STROBE
8 BIT
LACTH
OUTPUT
ENABLE
3 STATE
OUTPUTS
Truth table
QS
Q'S
SERIAL
OUTPUT
CLOCK
OUTPUT
ENABLE
STROBE
SERIAL
IN
H
H
L
H
H
H
H
L
X
L
X
X
H
X
X
H
H
X
Parallel Output
Q1
Qn
L
Qn-1
H
Qn-1
NC
NC
Z
Z
NC
NC
Z
Z
Serial Output
Qs
Q's
Q7
NC
Q7
NC
Q7
NC
Q7
NC
NC
Qs
NC
Qs
Q1
Q8
PARALLEL OUTPUTS
○ Switching characteristics
ｔWH
CLOCK
50%
50%
DATA
ｔsu
ｔh
STROBE
50%
tWL
tr tf
90%
10%
OUTPUT
ENABLE
Q1～Q7
QS
tPLH
tPHL
50% 90% 90% 50%
10%
10%
tTLH
tTHL
tpLH
50%
tPLH
50%
50%
tPHZ
90%
tpLH
QS’S'
50%
tPZH
10%
50%
tPLZ
10%
tPHL
50%
tPZL
90%
tpHL
50%
●Description of BU4538B series model
Function: Dual high accuracy monostable multivibrator
1) Description of operation
BU4538B is a re-triggerable monostable multi vibrator. Triggering is possible from either edge of the rise time and fall time
of input pulse. Output pulse setting is determined by the time constant (Rx · Cx) of external Rx and Cx.
Recommended output pulse amplitude is 200[μs]~1[s].
(Cautions on use: In case of system power down, etc., electric charge accumulated in the capacity Cx is discharged to the
VDD terminal through protective diode of 2 pins of 14 pins. When the electric current due to accumulated electric charge
exceeds 10[mA], IC may be destructed. When a large capacity Cx is used, electric current flowing into the IC can be
restricted by inserting the diode Dx.)
PIN description
PIN arrangement
Block diagram
T1A 1
T2A 2
CDA 3
AA 4
BA 5
BA
CD
C HA
T1
T2
QQ
BA
16 VDD
VDD
15 T1B
DX
RX
14 T2B
13 CDB
CX
12 AB
VDD
Vref1
Enable
Vref2
Enable
R
Q
Q
Output
Latch
S
Q
Q
PIN No. Symbol I/O
1
T1A ―
2
T2A ―
3
CDA I
4
AA I
5
BA I
Function
Passive component
connection pin 1(CHA)
Passive component
connection pin 2(CHA)
Reset input (CHA)
Input A(CHA)
Input B(CHA)
QA 6
QA 7
VSS 8
CD
CHB
T1
T2
QQ
11 BB
A
B
10 QB
CD
9 QB
Control
S Q Reset Latch
Q
R
6
QA O
Output Q(CHA)
7
QAB O
Output QB(CHA)
8
VSS ―
Power supply(-)
9
QBB O
Output QB(CHB)
10
QB O
Output Q(CHB)
Truth table
11
BB I
Input B(CHB)
INPUT
A
B
CD
H
H
L
H
OUTPUT
Q
Q
L
H
12
AB I
Input A(CHB)
13 CCB I
Reset input (CHB)
14
T2B
―
Passive component
connection pin 1(CHB)
H
H
L
H
L
H
15
T1B
―
Passive component
connection pin 2(CHB)
X
H
L
L
H
16 VDD ―
Power supply (+)
X：Don't Care
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14/17
2009.06 - Rev.A
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