BU4015B Просмотр технического описания (PDF) - ROHM Semiconductor
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BU4015B Datasheet PDF : 18 Pages
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BU4015B,BU4015BF,BU4021B,BU4021BF,
BU4094BC,BU4094BCF,BU4094BCFV,BU4538B,BU4028B
Technical Note
●Description of BU4021B series model
Function: 8-stage static shift register
1) Description of operation
BU4021B is an 8-bit static shift register capable of parallel input/series output and series input/series output. In parallel
operation, DS (data) being asynchronous with the clock is inputted into each F/F and obtained at output.
In series operation, DS (data) is triggered by clock.
When P/S input level is “H”, parallel operation is effective, and when P/S input level is “L”, series operation is effective.
PIN arrangement
Block diagram
P8 1
Q6 2
Q8 3
P4 4
P3 5
P2 6
P1 7
VSS 8
P8
P7
Q6
P6
Q8
Q5
P4
Q7
P3
DS
P2
CLOCK
P1
P/S
16 VDD P/S
D
15 P7
14 P6 CLOCK
13 P5
12 Q7
11 DS
10 CLOCK
9 P/S
P1 P2 P3 P4 P5 P6 P7 P8
D Q DQ DQ DQ DQ DQ DQ D
C
C
C
C
C
CQ CQ CQ
Q
Q
Q
Truth table
CLOCK D RESET Q0 Q1 Q2 Q3
L
L
L Q0 Q1 Q2
H
L
H Q0 Q1 Q2
X
L
No Change
X
X
H
L LLL
X：Don't Care
CLOCK DS
X
X
X：Don't Care
**:：QQ66,Q, Q77,Q,Q88: はou外ts部ide
P/S Dm
HL
HH
Qm*
L
H
PIN description
PIN No. Symbol
1
P8
2
Q6
3
Q8
4
P4
5
P3
6
P2
7
P1
8
VSS
9
P/S
10 CLOCK
11
DS
12
Q7
13
P5
14
P6
15
P7
16
VDD
I/O
Function
I Parallel data input 8
O
Output 6
O
Output 8
I Parallel data input 4
I Parallel data input 3
I Parallel data input 2
I Parallel data input 1
― Power supply(-)
I
Parallel/Serial
I
Clock input
I Serial data input
O
Output 7
I Parallel data input 5
I Parallel data input 6
I Parallel data input 7
― Power supply (+)
●Description of BU4094BC series model
Function: Dual 4-bit static shift register
1) Description of operation
BU4094BC is an 8-stage shift/store register provided in each stage with a data latch with 3-state output. Data read into
shift register is read into the latch during the fall time of asynchronous STROBE input, and in the data transfer mode,
output can be held. Data is passed through the latch and outputted when the STROBE is in “H” level. Because the parallel
output becomes high impedance when the OUTPUT ENABLE terminal is set to “L” level by 3-state, the parallel output can
be connected directly with the 8-bit pass line.
PIN arrangement
STROBE 1
SERIAL
IN
2
CLOCK 3
Q1 4
Q2 5
Q3 6
Q4 7
VSS 8
S TROB E
S E RIA
IN
O UTP UT
ENABLE
CLOCK
Q5
Q1
Q6
Q2
Q7
Q3
Q8
Q4
Q'S
QS
16 VDD
15
OUTPUT
ENABLE
14 Q5
13 Q6
12 Q7
11 Q8
10 Q'S
9 QS
PIN description
PIN No. Symbol I/O
1
STROBE I
2
SERIALIN I
3
CLOCK
I
4
Q1
O
5
Q2
O
6
Q3
O
7
Q4
O
8
VSS
―
9
QS
O
10
Q’S
O
11
Q8
O
12
Q7
O
13
Q6
O
14
Q5
O
15
ENABLE I
16
VDD
―
Function
Latch input
Data input
Clock input
Parallel data input Q1
Parallel data input Q2
Parallel data input Q3
Parallel data input Q4
Power supply(-)
Serial data output QS
Serial data output Q’S
Parallel data output Q8
Parallel data output Q7
Parallel data output Q6
Parallel data output Q5
Output enable
Power supply (+)
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13/17
2009.06 - Rev.A
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