HD74CDC857 Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics

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HD74CDC857

3.3/2.5-V Phase-lock Loop Clock Driver

Hitachi -> Renesas Electronics 

HD74CDC857

3.3/2.5-V Phase-lock Loop Clock Driver

ADE-205-222E (Z)

6th. Edition

July 1999

Description

The HD74CDC857 is a high-performance, low-skew, low-jitter, phase locked loop clock driver. It is

specifically designed for use with DDR (Double Data Rate) synchronous DRAMs.

Features

• Supports 100 MHz to 150 MHz operation range *1

• Distributes one differential clock input pair to ten differential clock outputs pairs

• SSTL_2 (Stub Series Terminated Logic) differential inputs and LVCMOS reset (G) input

• Supports spread spectrum clock

• External feedback pins (FBIN, FBIN) are used to synchronize the outputs to the clock input

• Supports both 3.3 V/2.5V analog supply voltage (AVCC), and 2.5 V VDDQ

• No external RC network required

• Sleep mode detection

• 48pin TSSOP (Thin Shrink Small Outline Package)

Note: 1. 200 MHz (Max) ver. will be available by 4Q/’99

Function Table

Inputs

:

G

CLK

CLK

:

L

L

H

:

L

H

L

:

H

L

H

:

H

H

L

:

X

0 MHz 0 MHz :

H : High level

L : Low level

Z : High impedance

X : Don’t care

Outputs

Y

Y

Z

Z

Z

Z

L

H

H

L

Z

Z

:

PLL

FBOUT FBOUT

Z

Z

:

off

Z

Z

:

off

L

H

:

run

H

L

:

run

Z

Z

:

off

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