RV5C338A-E2 Просмотр технического описания (PDF) - RICOH Co.,Ltd.

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RV5C338A-E2

3-WIRE SERIAL INTERFACE REAL-TIME CLOCK ICS WITH VOLTAGE MONITORING FUNCTION

RICOH Co.,Ltd. 

R×5C338A

Relation Between the Mode Waveform and the CTFG Bit

• Pulse mode

CTFG bit

INTR pin

Approx. 92µs

(Increment of second counter)

Rewriting of the second counter

*) In the pulse mode, the increment of the second counter is delayed by approximately 92 µs from the falling edge of clock pulses. Consequently, time

readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second.

Rewriting the second counter will reset the other time counters of less than 1 second, driving the INTR pin low.

• Level mode

CTFG bit

INTR pin

Setting CTFG bit to 0

Setting CTFG bit to 0

(Increment of

second counter)

5. 32-kHz Clock Output

(Increment of

second counter)

(Increment of

second counter)

32.768-kHz clock pulses are output from the 32KOUT pin when either the CLEN1 bit in the control register 2 or the

CLEN2 bit in the control register 1 is set to 0 when the CLKC pin is set to high. If the conditions described above

are not satisfied, the output is set to high.

CLEN1

(D3 at Address Fh)

CLEN2

(D4 at Address Eh)

CLKC pin output

32KOUT pin output

(CMOS output)

1

*

0 (Default)

*

1

*

*

0 (Default)

*

“L”

0

1

Clock pulses

1

The 32KOUT pin output is synchronized with the CLEN1, CLEN2 bit, and CLKC pin settings as illustrated in the tim-

ing chart below.

CLKC pin or

CLEN1 or CLEN2 bit setting

32KOUT pin output

MAX. 76.3µs

37

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