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RV5C338A-E2

3-WIRE SERIAL INTERFACE REAL-TIME CLOCK ICS WITH VOLTAGE MONITORING FUNCTION

RICOH Co.,Ltd. 

R×5C338A

4. Alarm and Periodic Interrupt

The R×5C338A incorporate the alarm circuit and the periodic interrupt circuit that are configured to generate alarm

signals and periodic interrupt signals, respectively, for output from the INTR pin as described below.

1)Alarm Circuit

The alarm interrupt circuit is configured to generate alarm signals for output from the INTR, which is driven low

(enabled) upon the occurrence of a match between current time read by the time counters (the day-of-week, hour,

and minute counters) and alarm time preset by the alarm registers (the Alarm_W registers intended for the day-

of-week, hour, and minute digit settings and the Alarm_D registers intended for the hour and minute digit set-

tings).

2)Periodic Interrupt Circuit

The periodic interrupt circuit is configured to generate either clock pulses in the pulse mode or interrupt signals

in the level mode for output from the INTR pin depending on the CT2, CT1, and CT0 bit settings in the control reg-

ister 1.

The above two types of interrupt signals are monitored by the flag bits (i.e. the WAFG, DAFG, and CTFG bits in the

control register 2) and enabled or disabled by the enable bits (i.e. the WALE, DALE, CT2, CT1, and CT0 bits in the

control register 1) as listed in the table below.

Alarm signals

(under control of Alarm_W registers)

Alarm signals

(under control of Alarm_D registers)

Periodic interrupt signals

Flag bits

WAFG bit

(D1 at Address Fh)

DAFG bit

(D0 at Address Fh)

CTFG bit

(D2 at Address Fh)

Enable bits

WALE bit

(D7 at Address Eh)

DALE bit

(D6 at Address Eh)

CT2, CT1, and CT0 bits (D2 to D0 at Address Eh)

(these bit settings of 0 disable the periodic interrupt circuit)

· At power-on, when the WALE, DALE, CT2, CT1, and CT0 bits are set to 0 in the control register 1, the INTR pin is

driven high (disabled).

· When two or more types of interrupt signals are output simultaneously from the INTR pin, the output from the

INTR pin becomes an OR waveform of their negative logic.

Example: Combined Output of Alarm Interrupt Signals from the INTR pin Under Control of Alarm_D and

Alarm_W Registers

Alarm_W

Alarm_D

INTR

In this event, which type of interrupt signal is output from the INTR pin can be confirmed by reading the

WAFG, DAFG, and CTFG bit settings in the control register 2.

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