W981216BH-75(2000) Просмотр технического описания (PDF) - Winbond

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W981216BH-75
(Rev.:2000)

2M x 4 BANKS x 16 BIT SDRAM

Winbond 

W981216BH

PIN DESCRIPTION

PIN NUMBER PIN NAME

FUNCTION

DESCRIPTION

23 − 26, 22,

29 − 35

20, 21

2, 4, 5, 7, 8,

10, 11, 13, 42,

44, 45, 47, 48,

50, 51, 53

19

18

17

16

A0 − A11

BS0, BS1

DQ0 −

DQ15

CS

RAS

CAS

WE

Address

Bank Select

Data Input/

Output

Multiplexed pins for row and column address.

Row address: A0 − A11. Column address: A0 − A8.

Select bank to activate during row address latch time,

or bank to read/write during address latch time.

Multiplexed pins for data output and input.

Chip Select

Disable or enable the command decoder. When

command decoder is disabled, new command is

ignored and previous operation continues.

Row Address

Strobe

Command input. When sampled at the rising edge of

the clock, RAS , CAS and WE define the

operation to be executed.

Column Address Referred to RAS

Strobe

Write Enable Referred to RAS

39, 15

38

37

1, 14, 27

28, 41, 54

3, 9, 43, 49

6, 12, 46, 52

36, 40

UDQM/

LDQM

CLK

CKE

VCC

VSS

VCCQ

VSSQ

NC

Input/Output

Mask

Clock Inputs

Clock Enable

Power (+3.3V)

Ground

Power (+3.3V)

for I/O Buffer

Ground for I/O

Buffer

No Connection

The output buffer is placed at Hi-Z (with latency of 2)

when DQM is sampled high in read cycle. In write

cycle, sampling DQM high will block the write

operation with zero latency.

System clock used to sample inputs on the rising edge

of clock.

CKE controls the clock activation and deactivation.

When CKE is low, Power Down mode, Suspend mode

or Self Refresh mode is entered.

Power for input buffers and logic circuit inside DRAM.

Ground for input buffers and logic circuit inside DRAM.

Separated power from VCC, used for output buffers to

improve noise.

Separated ground from VSS, used for output buffers to

improve noise.

No connection

Publication Release Date: October 2000

-3-

Revision A1

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