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AN-136

A NEW GENERATION OF TAG SRAMS—THE IDT71215 AND IDT71216

Integrated Device Technology 

A NEW GENERATION OF TAG SRAMS—THE IDT71215 AND IDT71216

APPLICATION NOTE AN-136

A31 - A3

PENTIUM

µP

BRDY

W/R

A17 - A5

IDT71215

TAG RAM

A29 - A18

ADDR (12:0) TAG (11:0)

ADDR (13)

RESET

BRDY

W/R

MATCH

3

STATUSOUT

3

STATUSIN

VCC

CS2

BRDYOE

CS1

OES

SFUNC

BRDYH

BRDYIN

WES

WET

OET

PWRDN

VARIOUS CONTROL SIGNALS

CHIP SET

MATCH

STATUS

STATUS

BRDYH

BRDY

WES

WET

OET

PWRDN

A17 - A3

DATA RAMS

ADDR

CACHE READ

and WRITE

IDT71V432

32K x 32

I/Os

MAIN MEMORY READ/WRITE

D63 - D0

Figure 11: Pentium / 71215 Example of 256 KB Cache

When changing the depth of the cache (and Tag RAM), the

TAG field shifts accordingly, so that it remains contiguous with

the address field. The example in Figure 11 uses only half of

a 71215, and can be compared with Figures 1 and 12. It shows

a 256KB cache for the Pentium, uses the BRDY pass-through

option from Figure 10, and maps 1GB of main memory into the

cache. Two 32Kx32 burst SRAMs are shown as the cache

data RAM.

3176 drw 11

9

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