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AN-1077

PFC Converter Design with IR1150 One Cycle Control IC

International Rectifier 

Application Note AN-1077

ripple current at fSW, peak current in the power switch

and EMI

However the trade-off here is an increased induc-

tance value to support the reduced ripple current,

resulting in increased size and cost.

Care must be taken for a given core selection

within a given design that the core does not saturate

at peak current levels.

Conversely, a higher value of allowable ripple cur-

rent, while resulting in a lower required inductor value,

will negatively impact performance in the areas previ-

ously pointed out.

Cost trade-offs are typical for core materials vs.

dissipation, temperature, and inductance roll off with

increasing current levels. Consult core manufac-

turer’s data books and application notes for detailed

inductor design considerations. Detailed inductor

design is beyond the scope of this application note.

Output Capacitor Requirements

Output Capacitor design in PFC converters is typi-

cally based on hold up time requirements. Typically,

with a proper design, ripple voltage and current in the

capacitor will not be an issue.

Typical values of capacitor for PFC applications

are 1µF to 2µF per watt of output power.

COUT ( MIN

)

=

2 ⋅ PO ⋅ ∆t

VO 2 − VO( MIN

2

)

(9)

COUT ( MIN )

=

2 ⋅ 300W ⋅ 30ms

( 385V )2 − ( 285V )2

=

269µF

Minimum capacitor value must be derated for ca-

pacitor tolerance, -20% in this case, in order to guar-

antee minimum capacitance requirement is satisfied,

thus assuring minimum hold up time.

COUT

= COUT (MIN )

1 − ∆CTOL

=

269µF

1 − 0.2

= 336µF

Standard value of 330µF is used in this case.

CONTROL SECTION DESIGN

Output Voltage Divider

Output voltage of the converter is set by voltage

divider RFB1, RFB2, and RFB3.

The total impedance of this divider string should

be selected high enough in value so as to reduce

power dissipation in divider. This is of particular con-

cern in terms of meeting stringent standby power

specifications, and beneficial in optimizing overall

system efficiency.

Practical limits do exist however on the maximum

impedance of the divider string. The resistor values

must not be selected so high as to introduce exces-

sive additional voltage error to the output voltage error

amplifier resulting from input bias currents of the am-

plifier.

A reasonable compromise for divider string overall

impedance is a target of approximately 1MΩ.

RFB1 and RFB2 are typically split equally in value to

create the upper resistor in the divider to keep the

maximum voltage across each resistor within the volt-

age rating of these devices, (typically 250V).

Divider resistors are selected with a ±1% tolerance

in order to minimize output voltage set point error.

The resistor tolerances will stack up in addition to

tolerance of the error amplifier reference and the error

introduced to the error amplifier due to input bias cur-

rents and input offset voltage.

RFB1 = RFB2 = 499KΩ, 1% tolerance.

This is a standard 1% value.

RFB3

=

VREF ( RFB1 + RFB2

(Vout VREF )

)

(10)

RFB3

=

7.0V ( 998K )

( 385V - 7.0V )

=

18.48KΩ

(use standard value RFB3 = 18.5kΩ)

Calculate new VO value based on actual resistor

values

International Rectifier Technical Assistance Center:

USA ++1 310 252 7105 Europe ++44 (0)208 645 8015 7 of 18

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