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AM7990

Serial Interface Adapter (SIA)

Advanced Micro Devices 

last rising edge of the message to INTCARR deassert

allows the last bit to be strobed by RCLK and trans-

ferred by the LANCE without an extra bit at the end of

the message. When RENA deasserts (see Receive

Timing—End of Reception waveform diagrams), a

RENA hold-off timer inhibits RENA assertion for at

least 120 ns.

Data Decoding

The data receiver is a comparator with clocked output

to minimize noise sensitivity to the Receive± inputs.

Input error (VIRD) is less than ±35 mV to minimize sen-

sitivity to input rise and fall time. RCLK strobes the data

receiver output at 1/4 bit time to determine the value of

the Manchester bit and clocks the data out at RX on the

following RCLK. The data receiver also generates the

signal used for phase detector comparison to the inter-

nal Am7992B VCO.

Differential l/O Terminations

The differential input for the Manchester data

(Receive±) is externally terminated by two 40.2-ohm

±1% resistors and one optional common-mode bypass

capacitor. The differential input impedance, ZlDF and

the common-mode input, ZlCM, are specified so that the

Ethernet specification for cable termination impedance

is met using standard 1% resistor terminators. The Col-

lision± differential inputs are terminated in exactly the

same way as the receive inputs (see Figure 6).

Collision Detection

A transceiver detects collisions on the network and

generates a 10 MHz signal at the Collision± inputs. This

collision signal passes through an input stage that de-

tects signal levels and pulse duration. When the signal

is detected by the Am7992B, it sets the CLSN line

HIGH. This condition continues for approximately

160 ns after the last LOW-to-HlGH transition on

Collision±.

VCC

R1 510 Ω C1 680 pF

C2 20 pF

R2 3 KΩ

20 MHz

Parallel Mode.

Crystal 50 pF

0.005% Accuracy

100 pF

100 pF

1 CLSN

2 RX

3 RENA

4 RCLK

5 TSEL

6 GND1

7 GND2

8 X1

9 X2

10 TX

11 TCLK

12 TENA

Collision+ 24

Collision– 23

Receive+ 22

Receive– 21

TEST 20

VCC1 19

VCC2 18

PF 17

RF 16

GND3 15

Transmit+ 14

Transmit– 13

40.2 Ω 1%

40.2 Ω 1%

40.2 Ω 1%

40.2 Ω 1%

A

C4

B

0.1 µF

0.1 µF C5

VCC

4.7 µF

4700 pF

0.1 µF

0.1 µF

03378I-10

Notes:

1. Connect R1, R2, C1, C2 for 0 differential nontransmit. Connect to ground for logic 1 differential nontransmit.

2. Pin 20 shown for normal device operation.

3. The inclusion of C4 and C5 is necessary to reduce the common-mode loading on certain transceivers that are direct

coupled.

4. C2 reduces the amount of noise from the power supply and crosstalk from RCLK that can be coupled from TSEL through to

the transmit± outputs.

Figure 6. External Component Diagram

Am7992B

9

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