AK5354(2001) Просмотр технического описания (PDF) - Asahi Kasei Microdevices

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AK5354
(Rev.:2001)

Low Power 20bit ∆Σ ADC with PGA

Asahi Kasei Microdevices 

ASAHI KASEI

[AK5354]

n System Reset & Offset Calibration

The AK5354 should be reset once by bringing PDN pin “L” after power-up. The control register values are initialized by

PDN “L”.

Offset calibration starts by PDN pin “L” to “H”. It takes 4128/fs to offset calibration cycle. During offset calibration, the

ADC digital data outputs of both channels are forced to a 2’s compliment “0”. Output data of settles data equivalent for

analog input signal after offset calibration. IPGA is set MUTE during offset calibration and after offset calibration.

As a normal offset calibration may not be executed, nothing write at address 01H during offset calibration.

When offset calibration is executed once, the calibration memory is held even if each block is powered down (PM0 = “0”

or PM1 = “0”) by power management bits.

Power Supply

PDN pin

PDN pin may be “L” at power-up.

ADC Internal

State

PD

AIN

SDTO

Control register

INIT-2

4128/fs

CAL

GD

“0”data (4)

Normal

PM

GD (1)

4128/fs

INIT-1

(2) (3) “0”data

Idle Noise

Normal

Normal

GD

(1)

W rite to register

Inhibit-1 Inhibit-2

Normal

External clocks

(5)

(5)

The clocks may be stopped.

Figure 8. Power up / Power down Timing Example

• PD:

• PM:

• CAL:

• INIT-1:

• Inhibit-1:

• Inhibit-2:

Power-down state. ADC is output “0”.

Power-down state by Power Management bit. ADC is output “0”.

During offset calibration cycle. IPGA is set MUTE state.

Initializing all control registers.

Inhibits writing to all control registers.

Enable writing to control registers except address 01H.

Note: See “Register Definitions” about the condition of each register.

(1). Digital output corresponding to analog input and analog output corresponding to digital input have the group delay

(GD). Output signal gradually comes to settle to input signal during a group delay.

(2). If the analog signal does not be input, digital outputs have the offset to op-amp of input and some offset error of a

internal ADC.

(3). ADC output is “0” at power down.

(4). This figure shows that MUTE of IPGA is canceled during offset calibration. If MUTE of IPGA is canceled, SDTO

outputs Idle Noise.

(5). When the external clocks (MCLK, BCLK and LRCK) are stopped, the AK5354 should be in the power down

(PDN pin = “L” or PM1 bit = “0”) mode.

MS0054-E-01

- 10 -

2001/01

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