AK5354(2001) Просмотр технического описания (PDF) - Asahi Kasei Microdevices

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AK5354
(Rev.:2001)

Low Power 20bit ∆Σ ADC with PGA

Asahi Kasei Microdevices 

ASAHI KASEI

[AK5354]

n Timing of Control Register

The internal registers are written by the 3-wire µP interface pins: CSN, CCLK, CDTI. These data are included by Op-code

(3bit), Address (LSB-first, 5bit) and Control data (LSB-first, 8bit). A side of transmitted data is output to each bit by “↓”

of CCLK, a side of receiving data is input by “↑” of CCLK. Writing of data becomes effective by “↑” of CSN. CSN should

be held to “H” at no access.

Address except 00H ∼ 03H inhibits control of writing. And CCLK always need 16 edges of “↑” during CSN = “L”.

CSN

CCLK

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

CDTI

op0 op1 op2 A0 A1 A2 A3 A4 D0 D1 D2 D3 D4 D5 D6 D7

“*” “*” “1”

op0-op2: Op code (Fixed to “**1:WRITE”)

A0-A4: Register Address

D0-D7: Control data

Figure 9. Control Data Timing

n Register Map

Addr

00H

01H

02H

03H

Register Name

Input Select

Mode Control 1

Mode Control 2

Input Analog PGA Control

D7

0

0

MONO1

ZEIP

D6

0

0

MONO0

IPGA6

D5

0

0

ZTM1

IPGA5

D4

HPF

0

ZTM0

IPGA4

D3

RIN2

0

0

IPGA3

D2

RIN1

0

0

IPGA2

D1

LIN2

PM1

DIF

IPGA1

D0

LIN1

PM0

0

IPGA0

All registers are reset at PDN = “L”, then inhibits writing to all registers.

MS0054-E-01

- 11 -

2001/01

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