ADMC330 Просмотр технического описания (PDF) - Analog Devices
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ADMC330 Datasheet PDF : 20 Pages
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ADMC330
VC
VVIL
PWMSYNC
tVIL
TPWM – TCRST
VCMAX
TCRST
As a result, assuming ±10% variations in both the capacitance
and current source, the nominal capacitance value required at a
given PWM period is:
V1
CNOM
= (0.9 ×
ICONST )(T PWM
(1.1)(3.5)
– TCRST
)
The largest standard value capacitor that is less than this calcu-
lated value is chosen. Table III shows the appropriate standard
capacitor value to use for various PWM switching frequencies
t
assuming ± 10% variations in both the current source and ca-
pacitor tolerances. If required, more precise control of the ramp
voltage is possible by using higher precision capacitor compo-
nents, an external current source and/or series or parallel timing
capacitor combinations.
COMPARATOR
OUTPUT
Figure 6. Analog Input Block Operation
ADC Resolution
Because the operation of the ADC is intrinsically linked to the
PMW block, the effective resolution of the ADC is a function of
the PMW switching frequency. The effective ADC resolution is
determined by the rate at which the counter timer is clocked.
For a CLKIN period of tCK and a PWM period of TPWM, the
maximum count of the ADC is given by
Max Count = T PWM
tCK
For an assumed CLKIN frequency of 10 MHz, the effective
resolution of the ADC block is tabulated for various PWM
switching frequencies in Table II.
Table III. Timing Capacitor Selection
PWM Frequency
(kHz)
Timing Capacitor
(pF)
2.5–3.0
820
3.0–3.6
680
3.6–4.3
560
4.3–5.2
470
5.2–6.2
390
6.2–7.3
330
7.3–9.0
270
9.0–10.9
220
10.9–13.2
180
13.2–15.8
150
15.8–19.6
120
19.6–23.4
100
23.4–28.2
82
Table II. ADC Resolution Examples
PWM Frequency
(kHz)
Max Count
Effective Resolution
(Bits)
2.5
3980
≈12
4
2480
>11
8
1230
>10
18
535
>9
25
380
>8
External Timing Capacitor
In order to maximize the useful input voltage range and effective
resolution of the ADC, it is necessary to carefully select the
value of the external timing capacitor. For a given capacitance
value, CNOM, the peak ramp voltage is given by:
( ) V C max = ICONST
T PWM – TCRST
CNOM
where ICONST is the nominal current source value of 10.5 µA and
TCRST is the PWMSYNC pulsewidth. In selecting the capacitor
value, however, it is necessary to take into account the tolerance
of the capacitor and the variation of the current source value.
To ensure that the full input range of the ADC is utilized, it is
necessary to select the capacitor so that at the maximum capaci-
tance value and the minimum current source output, the ramp
voltage will charge to at least 3.5 V.
AUXILIARY PWM TIMERS OVERVIEW
The two auxiliary PWM timers can be used to produce analog
signal outputs when configured as PWM DACs. This allows the
ADMC330 to generate a reference for power factor correction
and supply an analog reference for other systems in the applica-
tion. They can also be used as supplementary PWM outputs for
other control circuits.
The PWM timers generate two fixed frequency edge-based
variable duty cycle PWM signals. The PWM frequency is
1/256 times HCLK, or 39 kHz. The duty cycle is based on a
user-supplied 8-bit value loaded into the AUX0 and AUX1
registers.
The timer output can range from 0% to 99.6%, where the num-
ber written to the register represents the high time. The values
are updated as soon as new values are written in the registers: if
the value is smaller than the present counter value the output
goes low, otherwise it stays high.
On RESET, the AUX0 and AUX1 registers are cleared to zero
and remain at zero until a new value is written.
PWM DAC Equation
The PWM output must be filtered in order to produce a low
frequency analog signal between 0 V to 4.98 V dc. For example,
a 2-pole filter with a 1.2 kHz cut off frequency will sufficiently
attenuate the PWM carrier. Figure 7 shows how the filter would
be applied.
–10–
REV. 0
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