ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
Data Sheet
0V OR 3V
D
GENERATOR1
50Ω
S1
CL = 50pF2
VCC
RL = 110Ω
OUT
1PPR = 250kHz, 50% DUTY CYCLE, tR ≤ 6.0ns, ZO = 50Ω.
2CL INCLUDES PROBE AND STRAY CAPACITANCE.
Figure 23. Driver Enable and Disable Times (tPZL, tPSL, tPLZ)
+1.5V
–1.5V
S3
VID R
GENERATOR1
50Ω
1kΩ
CL2
S1
VCC
S2
1PPR = 250kHz, 50% DUTY CYCLE, tR ≤ 6.0ns, ZO = 50Ω.
2CL INCLUDES PROBE AND STRAY CAPACITANCE.
Figure 25. Receiver Enable and Disable Times
GENERATOR1
50Ω
VID R
OUT
CL = 15pF2
1.5V
0
VCC
VOM = 2
1PPR = 250kHz, 50% DUTY CYCLE, tR ≤ 6.0ns, ZO = 50Ω.
2CL INCLUDES PROBE AND STRAY CAPACITANCE.
Figure 24. Receiver Propagation Delays
Rev. E | Page 12 of 20