ADG725 Просмотр технического описания (PDF) - Analog Devices

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ADG725

16-/32- Channel, Serially Controlled 4Ω 1.8 V to 5.5 V, ±2.5 V, Analog Multiplexers

Analog Devices 

ADG725/ADG731

A serial interface between the ADG725/ADG731 and the ADSP-

2191M SPORT is shown in Figure 5. In this interface example,

SPORT0 is used to transfer data to the switch. Transmission is

initiated by writing a word to the Tx Register after the SPORT

has been enabled. In a write sequence, data is clocked out on

each rising edge of the DSP’s serial clock and clocked into the

ADG725/ADG731 on the falling edge of its SCLK. The update

of each switch condition takes place automatically after the eighth

SCLK falling edge, regardless of the frame sync condition.

Communication between two devices at a given clock speed is

possible when the following specs are compatible: frame sync

delay and frame sync setup and hold, data delay and data setup

and hold, and SCLK width. The ADG725/ADG31 expects a

t4 (SYNC falling edge to SCLK falling edge set-up time) of 13 ns

minimum. Consult the ADSP-21xx User Manual for information

on clock and frame sync frequencies for the SPORT Register.

The SPORT Control Register should be set up as follows:

TFSW = 1, Alternate Framing

INVTFS = 1, Active Low Frame Signal

DTYPE = 00, Right Justify Data

ISCLK = 1, Internal Serial Clock

TFSR = 1, Frame Every Word

ITFS = 1, Internal Framing Signal

SLEN = 0111, 8-Bit Data-Word

TFS

ADSP-2191M*

DT

SYNC

ADG725/ADG731

DIN

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY

SCLK

Figure 5. ADSP-2191M to ADG725/ADG731 Interface

8051 to ADG725/ADG731 Interface

A serial interface between the ADG725/ADG731 and the 8051

is shown in Figure 6. TXD of the 8051 drives SCLK of the

ADG725/ADG731, while RXD drives the serial data line, DIN.

P3.3 is a bit-programmable pin on the serial port and is used to

drive SYNC.

The 8051 provides the LSB of its SBUF Register as the first bit

in the data stream. The user will have to ensure that the data in

the SBUF Register is arranged correctly as the switch expects

MSB first.

When data is to be transmitted to the switch, P3.3 is taken low.

Data on RXD is clocked out of the microcontroller on the rising

edge of TXD and is valid on the falling edge. As a result, no

glue logic is required between the ADG725/ADG731 and

microcontroller interface.

P3.3

80C51/80L51*

RXD

SYNC

ADG725/ADG731

DIN

TXD

*ADDITIONAL PINS OMITTED FOR CLARITY

SCLK

Figure 6. 8051 to ADG725/ADG731 Interface

MC68HC11 Interface to ADG725/ADG731

Figure 7 shows an example of a serial interface between the

ADG725/ADG731 and the MC68HC11 microcontroller. SCK

of the 68HC11 drives the SCLK of the mux, while the MOSI

output drives the serial data line, DIN. SYNC is driven from

one of the port lines, in this case PC7. The 68HC11 is config-

ured for Master Mode: MSTR = 1, CPOL = 0, and CPHA = 1.

When data is transferred to the part, PC7 is taken low, and data

is transmitted MSB first. Data appearing on the MOSI output is

valid on the falling edge of SCK.

PC7

MC68HC11*

MOSI

SYNC

ADG725/ADG731

DIN

SCK

*ADDITIONAL PINS OMITTED FOR CLARITY

SCLK

Figure 7. MC68HC11 Interface to ADG725/ADG731

APPLICATION CIRCUITS

ADG725/ADG731 in an Optical Network Control Loop

The ADG725/ADG731 can be used in optical network applica-

tions that have higher port counts and greater multiplexing

requirements. The ADG725/ADG731 are well suited to these

applications because they allow a single control circuit to con-

nect a higher number of channels without increasing board size

and design complexity.

In the circuit shown in Figure 8, the 0 V to 5 V outputs of the

AD5532HS are amplified to a range of 0 V to 180 V and then

used to control actuators that determine the position of MEMS

mirrors in an optical switch. The exact position of each mirror is

measured using sensors. The sensor readings are muxed using

the ADG731, a 32-channel switch, and fed back to a single-

channel 14-bit ADC (AD7894).

The control loop is driven by an ADSP-2191L, a 32-bit DSP

with an SPI compatible SPORT interface. It writes data to the

DAC, controls the multiplexer, and reads data from the ADC

via a 3-wire serial interface.

1

AD5532HS

32

1

MEMS

MIRROR

ARRAY 32

ADG731

AD7894

ADSP-2191M

Figure 8. Optical Network Control Loop

Expand the Number of Selectable Serial Devices Using the

ADG725/ADG731

The SYNC pin of the ADG725/ADG731 can be used to select

one of a number of multiplexers. All devices receive the same

serial clock and serial data, but only one device will receive the

–14–

REV. A

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